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Another Power4 scheduling tweak
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 26 Mar 2003 11:03:27 -0500
- Subject: Another Power4 scheduling tweak
* config/rs6000/power4.md: Allow delay between dispatch and
function units for simple instructions. Correct store units.
Allow branch to occupy as many dispatch slots as necessary.
Index: power4.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/power4.md,v
retrieving revision 1.6
diff -c -p -r1.6 power4.md
*** power4.md 28 Feb 2003 19:42:41 -0000 1.6
--- power4.md 20 Mar 2003 16:15:38 -0000
***************
*** 37,45 ****
(define_reservation "q1_power4" "du1_power4|du4_power4")
(define_reservation "q2_power4" "du2_power4|du3_power4")
! (define_reservation "lsq_power4" "((du1_power4|du4_power4),lsu1_power4)\
! |((du2_power4|du3_power4),lsu2_power4)")
(define_reservation "lsuq_power4"
"((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
--- 37,48 ----
(define_reservation "q1_power4" "du1_power4|du4_power4")
(define_reservation "q2_power4" "du2_power4|du3_power4")
+ (define_reservation "q4_power4" "du1_power4|du2_power4|du3_power4|du4_power4")
! (define_reservation "lsq_power4" "(q1_power4,lsu1_power4)\
! |(q2_power4,lsu2_power4)\
! |(du3_power4,nothing,lsu2_power4)\
! |(du4_power4,nothing,lsu1_power4)")
(define_reservation "lsuq_power4"
"((du1_power4+du2_power4),lsu1_power4+iu2_power4)\
***************
*** 51,67 ****
"(du1_power4+du2_power4+du3_power4+du4_power4),\
iu1_power4,(lsu2_power4+iu2_power4)")
! (define_reservation "iq_power4" "((du1_power4|du4_power4),iu1_power4)\
! |((du2_power4|du3_power4),iu2_power4)")
!
! (define_reservation "fpq_power4" "((du1_power4|du4_power4),fpu1_power4)\
! |((du2_power4|du3_power4),fpu2_power4)")
(define_reservation "vq_power4"
! "(du1_power4|du2_power4|du3_power4|du4_power4),vec_power4")
(define_reservation "vpq_power4"
! "(du1_power4|du2_power4|du3_power4|du4_power4),\
! vecperm_power4")
; Dispatch slots are allocated in order conforming to program order.
--- 54,74 ----
"(du1_power4+du2_power4+du3_power4+du4_power4),\
iu1_power4,(lsu2_power4+iu2_power4)")
! (define_reservation "iq_power4" "(q1_power4,iu1_power4)\
! |(q2_power4,iu2_power4)\
! |(du3_power4,nothing,iu2_power4)\
! |(du4_power4,nothing,iu1_power4)")
!
! (define_reservation "fpq_power4" "(q1_power4,fpu1_power4)\
! |(q2_power4,fpu2_power4)\
! |(du3_power4,nothing,fpu2_power4)\
! |(du4_power4,nothing,fpu1_power4)")
(define_reservation "vq_power4"
! "(q4_power4,vec_power4)|(q4_power4,nothing,vec_power4)")
(define_reservation "vpq_power4"
! "(q4_power4,vecperm_power4)\
! |(q4_power4,nothing,vecperm_power4)")
; Dispatch slots are allocated in order conforming to program order.
***************
*** 129,136 ****
(define_insn_reservation "power4-store" 1
(and (eq_attr "type" "store")
(eq_attr "cpu" "power4"))
! "((du1_power4|du4_power4),lsu1_power4,iu2_power4)\
! |((du2_power4|du3_power4),lsu2_power4,iu1_power4)")
(define_insn_reservation "power4-store-update" 1
(and (eq_attr "type" "store_u")
--- 136,143 ----
(define_insn_reservation "power4-store" 1
(and (eq_attr "type" "store")
(eq_attr "cpu" "power4"))
! "(q1_power4,lsu1_power4,iu1_power4)\
! |(q2_power4,lsu2_power4,iu2_power4)")
(define_insn_reservation "power4-store-update" 1
(and (eq_attr "type" "store_u")
***************
*** 145,152 ****
(define_insn_reservation "power4-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4"))
! "((du1_power4|du4_power4),lsu1_power4,fpu1_power4)\
! |((du2_power4|du3_power4),lsu2_power4,fpu2_power4)")
(define_insn_reservation "power4-fpstore-update" 1
(and (eq_attr "type" "fpstore_u")
--- 152,159 ----
(define_insn_reservation "power4-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4"))
! "(q1_power4,lsu1_power4,fpu1_power4)\
! |(q2_power4,lsu2_power4,fpu2_power4)")
(define_insn_reservation "power4-fpstore-update" 1
(and (eq_attr "type" "fpstore_u")
***************
*** 165,172 ****
(define_insn_reservation "power4-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power4"))
! "((du1_power4|du4_power4),lsu1_power4,vec_power4)\
! |((du2_power4|du3_power4),lsu2_power4,vec_power4)")
; Integer latency is 2 cycles
--- 172,179 ----
(define_insn_reservation "power4-vecstore" 1
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "power4"))
! "(q1_power4,lsu1_power4,vec_power4)\
! |(q2_power4,lsu2_power4,vec_power4)")
; Integer latency is 2 cycles
***************
*** 228,234 ****
(define_insn_reservation "power4-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power4"))
! "du5_power4,bpu_power4")
; Condition Register logical ops are split if non-destructive (RT != RB)
--- 235,245 ----
(define_insn_reservation "power4-branch" 2
(and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "power4"))
! "(du5_power4\
! |du4_power4+du5_power4\
! |du3_power4+du4_power4+du5_power4\
! |du2_power4+du3_power4+du4_power4+du5_power4\
! |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4")
; Condition Register logical ops are split if non-destructive (RT != RB)