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Re: [PATCH] CSE MEMs loaded in narrower modes
- From: kaih at khms dot westfalen dot de (Kai Henningsen)
- To: gcc-patches at gcc dot gnu dot org
- Date: 08 Mar 2003 08:22:00 +0200
- Subject: Re: [PATCH] CSE MEMs loaded in narrower modes
- Comment: Unsolicited commercial mail will incur an US$100 handling fee per received mail.
- Organization: Organisation? Me?! Are you kidding?
- References: <Pine.LNX.4.44.0303060621480.20707-100000@www.eyesopen.com>
roger at www dot eyesopen dot com (Roger Sayle) wrote on 06.03.03 in <Pine dot LNX dot 4 dot 44 dot 0303060621480 dot 20707-100000 at www dot eyesopen dot com>:
> Then thinking outside the box, I realized the problem could also be
> solved by loading "var" from memory in its original mode into a
> register, and then extracting the low part of the register. This
> representation is more convenient for GCC's RTL optimizers, and the
> conversion back to a HImode load would take place during combine.
> So good news, as hoped combine narrows the loads as appropriate and we
> don't lose anything in performance, and catch the optimization opportunity
> when available. Performance also remained the same on SPECfp2000 at -O2
> and both SPECint and SPECfp at -O3. The biggest surprise was the ~1%
> improvement in compiler performance at -O2:
Well ... another example for the perils of premature optimization ;-)
MfG Kai