Re: ARM - register liveness problem

[Laszlo Vidacs <lac at rgai dot hu>]

On Thu, 27 Feb 2003, Richard Henderson wrote:

> > I am writing a patch for ARM target. I would like to use register liveness
> > information during the peephole2 phase. The peep2_regno_dead_p() function
> > says that register r4 is live at instruction marked with (*) in the
> > example below, but i think it is dead because of the ldmfd instruction.
> > Why is it still considered live?
>
> You'll have to post the rtl involved, as well as your patch
> for us to be able to tell.
>

The problem is described in PR #9832
http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=9832

I think this could be solved in combine phase or using a peephole2(?)
The patch for peephole2, the preprocessed example source and the rtl after
flow2 is attached.

Here is the current state of the patch in arm.md:

;; omitting move into dead register
(define_peephole2
  [(set (match_operand:SI 0 "register_operand" "")
        (match_operator:SI 3 "logical_binary_operator"
              [(match_dup 0) (match_operand:SI 1 "reg_or_int_operand" "")] ))
   (set (match_operand:SI 2 "register_operand" "") (match_dup 0))]
  "TARGET_ARM && peep2_regno_dead_p(1, REGNO(operands[0]))"
  [(set (match_dup 2)
        (match_op_dup:SI 3 [(match_dup 0) (match_dup 1)]) )]
  ""
)

This peephole would replace
	and r4, r4, #255 @ 27
	mov r1, r4	 @ 29
into
	and r1, r4, #255

The set of matching operators can be wider (shiftable and shift
operators, so the appripriate functions must be written also).

Maybe the problem is caused by insn 47 (unspec_volatile)?

Regards,
Laszlo

Attachment: 01.s
Description: Text document

Attachment: arm.md.patch
Description: Text document

Attachment: 01.c.26.flow2
Description: Text document

Attachment: 01.i
Description: Text document