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[patch] h8300.md: Relax conditions for some insn patterns
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 28 Feb 2003 08:37:14 -0500 (EST)
- Subject: [patch] h8300.md: Relax conditions for some insn patterns
Hi,
Attached is a patch to relax conditions for some insn patterns.
void
foo (unsigned long *p)
{
if (*p & 0x800000)
bar ();
}
Currently, the above code turns into
_foo:
mov.b @(1,er0),r2l ; load one byte
mov.b #7,r3l ; shift 7 bits
.Llt1:
shlr.l er2
add #0xff,r3l
bne .Llt1
btst #0,r2l ; test bit 0
beq .L1
jsr @_bar
.L1:
rts
The reason for this bad code generation is that the pattern accepting
a bit test against memory rejects the test of bit 7, hoping that the
sign test will take over.
_foo:
mov.b @(1,er0),r0l
bge .L1
jsr @_bar
.L1:
rts
The patch accepts the test of bit 7 during the combiner phase and
later changes the bit test to the sign test by a peephole2.
Kazu Hirata
2003-02-28 Kazu Hirata <kazu at cs dot umass dot edu>
* config/h8300/h8300.md (*tst_extzv_bitqi_1_n): Accept the
test of bit 7.
(*tst_extzv_memqi_1_n): Likewise.
(a peephole2): New.
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.174
diff -u -r1.174 h8300.md
--- h8300.md 21 Feb 2003 14:46:11 -0000 1.174
+++ h8300.md 28 Feb 2003 01:46:00 -0000
@@ -592,8 +592,7 @@
[(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_operand" "r,U")
(const_int 1)
(match_operand 1 "const_int_operand" "n,n")))]
- "(TARGET_H8300H || TARGET_H8300S)
- && INTVAL (operands[1]) != 7"
+ "(TARGET_H8300H || TARGET_H8300S)"
"btst %Z1,%Y0"
[(set_attr "length" "2,8")
(set_attr "cc" "set_zn,set_zn")])
@@ -604,8 +603,7 @@
(match_operand 1 "const_int_operand" "n")))
(clobber (match_scratch:QI 2 "=&r"))]
"(TARGET_H8300H || TARGET_H8300S)
- && !EXTRA_CONSTRAINT (operands[0], 'U')
- && INTVAL (operands[1]) != 7"
+ && !EXTRA_CONSTRAINT (operands[0], 'U')"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -3513,6 +3511,27 @@
(label_ref (match_dup 2))
(pc)))]
"")
+
+(define_peephole2
+ [(set (cc0)
+ (zero_extract:SI (match_operand:QI 0 "register_operand" "")
+ (const_int 1)
+ (const_int 7)))
+ (set (pc)
+ (if_then_else (match_operator 1 "eqne_operator"
+ [(cc0) (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))]
+ "(TARGET_H8300H || TARGET_H8300S)"
+ [(set (cc0)
+ (match_dup 0))
+ (set (pc)
+ (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
+ (label_ref (match_dup 2))
+ (pc)))]
+ "operands[3] = ((GET_CODE (operands[1]) == EQ)
+ ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
+ : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
;; the equivalent with shorter sequences. Here is the summary. Cases