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[3.3/mainilne] Fix kernel misscopmiilation for hammer
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at cygnus dot com
- Date: Sat, 22 Feb 2003 22:57:05 +0100
- Subject: [3.3/mainilne] Fix kernel misscopmiilation for hammer
Hi,
this patch fixes nasty RTL sharing problem. The movabs patterns match
operand inside the MEM reference. When reloading happends the possibly
shared MEM reference is modified in place. For me this happent in a way
so DECL_RTL of global variable has been set into (mem:QI rax) that is
not good.
I don't see better way than avoid the reloading by restricting the
template into constants. Better ideas?
Sat Feb 22 22:54:07 CET 2003 Jan Hubicka <jh at suse dot cz>
* i386.md (movabs*): Restrict to first alternative
* i386.c (x86_64_movabs_operand): Prohibit non-immediate operands.
Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.401.2.19
diff -c -3 -p -r1.401.2.19 i386.md
*** i386.md 22 Feb 2003 21:22:54 -0000 1.401.2.19
--- i386.md 22 Feb 2003 21:53:22 -0000
***************
*** 1248,1277 ****
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabssi_1_rex64"
! [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
! (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
! "@
! movabs{l}\t{%1, %P0|%P0, %1}
! mov{l}\t{%1, %a0|%a0, %1}
! movabs{l}\t{%1, %a0|%a0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0,*,*")
! (set_attr "length_address" "8,0,0")
! (set_attr "length_immediate" "0,*,*")
(set_attr "memory" "store")
(set_attr "mode" "SI")])
(define_insn "*movabssi_2_rex64"
! [(set (match_operand:SI 0 "register_operand" "=a,r")
! (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
! "@
! movabs{l}\t{%P1, %0|%0, %P1}
! mov{l}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0,*")
! (set_attr "length_address" "8,0")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "SI")])
--- 1248,1272 ----
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabssi_1_rex64"
! [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i"))
! (match_operand:SI 1 "nonmemory_operand" "a"))]
"TARGET_64BIT"
! "movabs{l}\t{%1, %P0|%P0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
! (set_attr "length_immediate" "0")
(set_attr "memory" "store")
(set_attr "mode" "SI")])
(define_insn "*movabssi_2_rex64"
! [(set (match_operand:SI 0 "register_operand" "=a")
! (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i")))]
"TARGET_64BIT"
! "movabs{l}\t{%P1, %0|%0, %P1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "SI")])
***************
*** 1374,1403 ****
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabshi_1_rex64"
! [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
! (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
! "@
! movabs{w}\t{%1, %P0|%P0, %1}
! mov{w}\t{%1, %a0|%a0, %1}
! movabs{w}\t{%1, %a0|%a0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0,*,*")
! (set_attr "length_address" "8,0,0")
! (set_attr "length_immediate" "0,*,*")
(set_attr "memory" "store")
(set_attr "mode" "HI")])
(define_insn "*movabshi_2_rex64"
! [(set (match_operand:HI 0 "register_operand" "=a,r")
! (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
! "@
! movabs{w}\t{%P1, %0|%0, %P1}
! mov{w}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0,*")
! (set_attr "length_address" "8,0")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "HI")])
--- 1369,1393 ----
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabshi_1_rex64"
! [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i"))
! (match_operand:HI 1 "nonmemory_operand" "a"))]
"TARGET_64BIT"
! "movabs{w}\t{%1, %P0|%P0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
! (set_attr "length_immediate" "0")
(set_attr "memory" "store")
(set_attr "mode" "HI")])
(define_insn "*movabshi_2_rex64"
! [(set (match_operand:HI 0 "register_operand" "=a")
! (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i")))]
"TARGET_64BIT"
! "movabs{w}\t{%P1, %0|%0, %P1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "HI")])
***************
*** 1693,1722 ****
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsqi_1_rex64"
! [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
! (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
! "@
! movabs{b}\t{%1, %P0|%P0, %1}
! mov{b}\t{%1, %a0|%a0, %1}
! movabs{b}\t{%1, %a0|%a0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0,*,*")
! (set_attr "length_address" "8,0,0")
! (set_attr "length_immediate" "0,*,*")
(set_attr "memory" "store")
(set_attr "mode" "QI")])
(define_insn "*movabsqi_2_rex64"
! [(set (match_operand:QI 0 "register_operand" "=a,r")
! (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
! "@
! movabs{b}\t{%P1, %0|%0, %P1}
! mov{b}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0,*")
! (set_attr "length_address" "8,0")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "QI")])
--- 1683,1707 ----
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsqi_1_rex64"
! [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i"))
! (match_operand:QI 1 "nonmemory_operand" "a"))]
"TARGET_64BIT"
! "movabs{b}\t{%1, %P0|%P0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
! (set_attr "length_immediate" "0")
(set_attr "memory" "store")
(set_attr "mode" "QI")])
(define_insn "*movabsqi_2_rex64"
! [(set (match_operand:QI 0 "register_operand" "=a")
! (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i")))]
"TARGET_64BIT"
! "movabs{b}\t{%P1, %0|%0, %P1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "QI")])
***************
*** 2072,2101 ****
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsdi_1_rex64"
! [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
! (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
"TARGET_64BIT"
! "@
! movabs{q}\t{%1, %P0|%P0, %1}
! mov{q}\t{%1, %a0|%a0, %1}
! movabs{q}\t{%1, %a0|%a0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0,*,*")
! (set_attr "length_address" "8,0,0")
! (set_attr "length_immediate" "0,*,*")
(set_attr "memory" "store")
(set_attr "mode" "DI")])
(define_insn "*movabsdi_2_rex64"
! [(set (match_operand:DI 0 "register_operand" "=a,r")
! (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
"TARGET_64BIT"
! "@
! movabs{q}\t{%P1, %0|%0, %P1}
! mov{q}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0,*")
! (set_attr "length_address" "8,0")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "DI")])
--- 2057,2081 ----
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsdi_1_rex64"
! [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i"))
! (match_operand:DI 1 "nonmemory_operand" "a"))]
"TARGET_64BIT"
! "movabs{q}\t{%1, %P0|%P0, %1}"
! [(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
! (set_attr "length_immediate" "0")
(set_attr "memory" "store")
(set_attr "mode" "DI")])
(define_insn "*movabsdi_2_rex64"
! [(set (match_operand:DI 0 "register_operand" "=a")
! (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i")))]
"TARGET_64BIT"
! "movabs{q}\t{%P1, %0|%0, %P1}"
[(set_attr "type" "imov")
! (set_attr "modrm" "0")
! (set_attr "length_address" "8")
(set_attr "length_immediate" "0")
(set_attr "memory" "load")
(set_attr "mode" "DI")])
Index: i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.490.2.25
diff -c -3 -p -r1.490.2.25 i386.c
*** i386.c 22 Feb 2003 21:22:53 -0000 1.490.2.25
--- i386.c 22 Feb 2003 21:54:36 -0000
*************** x86_64_nonmemory_operand (op, mode)
*** 3129,3135 ****
return x86_64_sign_extended_value (op);
}
! /* Return nonzero if OP is nonmemory operand acceptable by movabs patterns. */
int
x86_64_movabs_operand (op, mode)
--- 3129,3137 ----
return x86_64_sign_extended_value (op);
}
! /* Return nonzero if OP is nonmemory operand acceptable by movabs patterns.
! The predicate must accept only constants as otherwise reload may in-place
! modify shared memory references in movabs* patterns. */
int
x86_64_movabs_operand (op, mode)
*************** x86_64_movabs_operand (op, mode)
*** 3137,3145 ****
enum machine_mode mode;
{
if (!TARGET_64BIT || !flag_pic)
! return nonmemory_operand (op, mode);
! if (register_operand (op, mode) || x86_64_sign_extended_value (op))
! return 1;
if (CONSTANT_P (op) && !symbolic_reference_mentioned_p (op))
return 1;
return 0;
--- 3139,3145 ----
enum machine_mode mode;
{
if (!TARGET_64BIT || !flag_pic)
! return immediate_operand (op, mode);
if (CONSTANT_P (op) && !symbolic_reference_mentioned_p (op))
return 1;
return 0;