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Re: Unit-at-time related PRs
- From: <tm_gccmail at mail dot kloo dot net>
- To: Zack Weinberg <zack at codesourcery dot com>
- Cc: Jim Wilson <wilson at redhat dot com>,Geoff Keating <geoffk at geoffk dot org>, Jan Hubicka <jh at suse dot cz>,gcc-patches at gcc dot gnu dot org
- Date: Thu, 20 Feb 2003 18:36:27 -0800 (PST)
- Subject: Re: Unit-at-time related PRs
On Thu, 20 Feb 2003 tm_gccmail at mail dot kloo dot net wrote:
> On Thu, 20 Feb 2003, Zack Weinberg wrote:
> > Jim Wilson <wilson at redhat dot com> writes:
> > > On some of the compact ISAs, e.g. SH, Thumb (ARM), MIPS16, the only
> > > addressing mode you have for getting to global data is pc-relative
> > > with an 8 bit offset. The only way to make this work is to have per
> > > function constant tables which are placed inside the function if the
> > > function is larger than 256 bytes.
> > I say this not knowing much about these ISAs, but my understanding is
> > that they are not register-starved, and register-indirect addressing
> > is available. Thus, what about an implementation similar to x86 PIC
> > mode, where a register is dedicated to hold the address of a shared
> > constant pool, and loaded at the beginning of each function?
> > zw
> Um. They are register-starved.
> The SH has 16 GP registers, but MIPS16 and Thumb have only eight available
> GP registers.
> So for MIPS16/Thumb, you would have:
> stack pointer
> frame pointer
> GOT pointer
> constant pool pointer
> ...and 4 GP registers left.
I forgot the "this" pointer for C++...so you're down to 3 available
Yes, I know the values can be spilled, but it's still rather tight.