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Fix last SSE bug
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at redhat dot com
- Date: Thu, 20 Feb 2003 23:04:08 +0100
- Subject: Fix last SSE bug
Last time I was too optimistic, but this one must be the last problem
and now GCC SSE implementation is simply perfect.
Thu Feb 20 22:42:00 CET 2003 Jan Hubicka <jh at suse dot cz>
* i386.c (builtin_description): Add __builtin_ia32_paddq and
__builtin_ia32_psubq. Fix __builtin_ia32_paddq128
and __builtin_ia32_psubq128.
* i386.h (IX86_BUILTIN_PADDQ, IX86_BUILTIN_PSUBQ): New.
* i386.md (addv*, mmx_ior*, mmx_xoe*, mmx_and*): Add missing '%'.
(mmx_adddi3, mmx_subdi3): New.
* mmintrin.h (_mm_add_si64, _mm_sub_si64): New.
* xmmintrin.h (_mm_movepi64_pi64): New.
(_mm_add_epi64, _mm_sub_epi64): fix.
(_mm_mul_pu16): Rename to...
(_mm_mul_su32): ... this one.
Index: i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.490.2.24
diff -c -3 -p -r1.490.2.24 i386.c
*** i386.c 16 Feb 2003 18:50:08 -0000 1.490.2.24
--- i386.c 20 Feb 2003 21:36:22 -0000
*************** static const struct builtin_description
*** 12499,12507 ****
--- 12502,12512 ----
{ MASK_MMX, CODE_FOR_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
{ MASK_MMX, CODE_FOR_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
{ MASK_MMX, CODE_FOR_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
+ { MASK_MMX, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
{ MASK_MMX, CODE_FOR_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
{ MASK_MMX, CODE_FOR_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
{ MASK_MMX, CODE_FOR_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
+ { MASK_MMX, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
{ MASK_MMX, CODE_FOR_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
{ MASK_MMX, CODE_FOR_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
*************** static const struct builtin_description
*** 12622,12632 ****
{ MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
{ MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
{ MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
! { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
{ MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
{ MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
{ MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
! { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
{ MASK_MMX, CODE_FOR_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
{ MASK_MMX, CODE_FOR_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
--- 12628,12638 ----
{ MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
{ MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
{ MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
! { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
{ MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
{ MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
{ MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
! { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
{ MASK_MMX, CODE_FOR_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
{ MASK_MMX, CODE_FOR_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
Index: i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.305.2.11
diff -c -3 -p -r1.305.2.11 i386.h
*** i386.h 16 Feb 2003 18:50:08 -0000 1.305.2.11
--- i386.h 20 Feb 2003 21:36:23 -0000
*************** enum ix86_builtins
*** 2172,2177 ****
--- 2175,2181 ----
IX86_BUILTIN_PADDB,
IX86_BUILTIN_PADDW,
IX86_BUILTIN_PADDD,
+ IX86_BUILTIN_PADDQ,
IX86_BUILTIN_PADDSB,
IX86_BUILTIN_PADDSW,
IX86_BUILTIN_PADDUSB,
*************** enum ix86_builtins
*** 2179,2184 ****
--- 2183,2189 ----
IX86_BUILTIN_PSUBB,
IX86_BUILTIN_PSUBW,
IX86_BUILTIN_PSUBD,
+ IX86_BUILTIN_PSUBQ,
IX86_BUILTIN_PSUBSB,
IX86_BUILTIN_PSUBSW,
IX86_BUILTIN_PSUBUSB,
Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.401.2.18
diff -c -3 -p -r1.401.2.18 i386.md
*** i386.md 19 Feb 2003 16:18:50 -0000 1.401.2.18
--- i386.md 20 Feb 2003 21:36:26 -0000
***************
*** 20211,20217 ****
(define_insn "addv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
! (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddb\t{%2, %0|%0, %2}"
--- 20234,20240 ----
(define_insn "addv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
! (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddb\t{%2, %0|%0, %2}"
***************
*** 20220,20226 ****
(define_insn "addv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
! (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddw\t{%2, %0|%0, %2}"
--- 20243,20249 ----
(define_insn "addv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
! (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddw\t{%2, %0|%0, %2}"
***************
*** 20229,20244 ****
(define_insn "addv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
! (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
(define_insn "ssaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
! (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsb\t{%2, %0|%0, %2}"
--- 20252,20278 ----
(define_insn "addv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
! (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
+ (define_insn "mmx_adddi3"
+ [(set (match_operand:DI 0 "register_operand" "=y")
+ (unspec:DI
+ [(plus:DI (match_operand:DI 1 "register_operand" "%0")
+ (match_operand:DI 2 "nonimmediate_operand" "ym"))]
+ UNSPEC_NOP))]
+ "TARGET_MMX"
+ "paddq\t{%2, %0|%0, %2}"
+ [(set_attr "type" "mmxadd")
+ (set_attr "mode" "DI")])
+
(define_insn "ssaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
! (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsb\t{%2, %0|%0, %2}"
***************
*** 20247,20253 ****
(define_insn "ssaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
! (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsw\t{%2, %0|%0, %2}"
--- 20281,20287 ----
(define_insn "ssaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
! (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsw\t{%2, %0|%0, %2}"
***************
*** 20256,20262 ****
(define_insn "usaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
! (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusb\t{%2, %0|%0, %2}"
--- 20290,20296 ----
(define_insn "usaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
! (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusb\t{%2, %0|%0, %2}"
***************
*** 20265,20271 ****
(define_insn "usaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
! (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusw\t{%2, %0|%0, %2}"
--- 20299,20305 ----
(define_insn "usaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
! (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusw\t{%2, %0|%0, %2}"
***************
*** 20299,20304 ****
--- 20333,20349 ----
[(set_attr "type" "mmxadd")
(set_attr "mode" "DI")])
+ (define_insn "mmx_subdi3"
+ [(set (match_operand:DI 0 "register_operand" "=y")
+ (unspec:DI
+ [(minus:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand:DI 2 "nonimmediate_operand" "ym"))]
+ UNSPEC_NOP))]
+ "TARGET_MMX"
+ "psubq\t{%2, %0|%0, %2}"
+ [(set_attr "type" "mmxadd")
+ (set_attr "mode" "DI")])
+
(define_insn "sssubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
(ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
***************
*** 20402,20408 ****
(define_insn "mmx_iordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
! [(ior:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX"
--- 20447,20453 ----
(define_insn "mmx_iordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
! [(ior:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX"
***************
*** 20413,20419 ****
(define_insn "mmx_xordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
! [(xor:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX"
--- 20458,20464 ----
(define_insn "mmx_xordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
! [(xor:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX"
***************
*** 20436,20442 ****
(define_insn "mmx_anddi3"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
! [(and:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX"
--- 20481,20487 ----
(define_insn "mmx_anddi3"
[(set (match_operand:DI 0 "register_operand" "=y")
(unspec:DI
! [(and:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "nonimmediate_operand" "ym"))]
UNSPEC_NOP))]
"TARGET_MMX"
***************
*** 21863,21869 ****
(define_insn "addv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
! (plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddb\t{%2, %0|%0, %2}"
--- 21940,21946 ----
(define_insn "addv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
! (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddb\t{%2, %0|%0, %2}"
***************
*** 21872,21878 ****
(define_insn "addv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
! (plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddw\t{%2, %0|%0, %2}"
--- 21949,21955 ----
(define_insn "addv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
! (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddw\t{%2, %0|%0, %2}"
***************
*** 21881,21887 ****
(define_insn "addv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
! (plus:V4SI (match_operand:V4SI 1 "register_operand" "0")
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddd\t{%2, %0|%0, %2}"
--- 21958,21964 ----
(define_insn "addv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
! (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddd\t{%2, %0|%0, %2}"
***************
*** 21890,21896 ****
(define_insn "addv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
! (plus:V2DI (match_operand:V2DI 1 "register_operand" "0")
(match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddq\t{%2, %0|%0, %2}"
--- 21967,21973 ----
(define_insn "addv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
! (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
(match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddq\t{%2, %0|%0, %2}"
***************
*** 21899,21905 ****
(define_insn "ssaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
! (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsb\t{%2, %0|%0, %2}"
--- 21976,21982 ----
(define_insn "ssaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
! (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsb\t{%2, %0|%0, %2}"
***************
*** 21908,21914 ****
(define_insn "ssaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
! (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsw\t{%2, %0|%0, %2}"
--- 21985,21991 ----
(define_insn "ssaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
! (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsw\t{%2, %0|%0, %2}"
***************
*** 21917,21923 ****
(define_insn "usaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
! (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusb\t{%2, %0|%0, %2}"
--- 21994,22000 ----
(define_insn "usaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
! (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusb\t{%2, %0|%0, %2}"
***************
*** 21926,21932 ****
(define_insn "usaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
! (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusw\t{%2, %0|%0, %2}"
--- 22003,22009 ----
(define_insn "usaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
! (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusw\t{%2, %0|%0, %2}"
Index: mmintrin.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/mmintrin.h,v
retrieving revision 1.4
diff -c -3 -p -r1.4 mmintrin.h
*** mmintrin.h 19 Oct 2002 08:48:37 -0000 1.4
--- mmintrin.h 20 Feb 2003 21:36:26 -0000
*************** _mm_add_pi32 (__m64 __m1, __m64 __m2)
*** 160,165 ****
--- 160,172 ----
return (__m64) __builtin_ia32_paddd ((__v2si)__m1, (__v2si)__m2);
}
+ /* Add the 64-bit values in M1 to the 64-bit values in M2. */
+ static __inline __m64
+ _mm_add_si64 (__m64 __m1, __m64 __m2)
+ {
+ return (__m64) __builtin_ia32_paddq ((long long)__m1, (long long)__m2);
+ }
+
/* Add the 8-bit values in M1 to the 8-bit values in M2 using signed
saturated arithmetic. */
static __inline __m64
*************** static __inline __m64
*** 211,216 ****
--- 218,230 ----
_mm_sub_pi32 (__m64 __m1, __m64 __m2)
{
return (__m64) __builtin_ia32_psubd ((__v2si)__m1, (__v2si)__m2);
+ }
+
+ /* Add the 64-bit values in M1 to the 64-bit values in M2. */
+ static __inline __m64
+ _mm_sub_si64 (__m64 __m1, __m64 __m2)
+ {
+ return (__m64) __builtin_ia32_psubq ((long long)__m1, (long long)__m2);
}
/* Subtract the 8-bit values in M2 from the 8-bit values in M1 using signed
Index: xmmintrin.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/xmmintrin.h,v
retrieving revision 1.19.2.1
diff -c -3 -p -r1.19.2.1 xmmintrin.h
*** xmmintrin.h 12 Jan 2003 14:24:22 -0000 1.19.2.1
--- xmmintrin.h 20 Feb 2003 21:36:26 -0000
*************** _mm_storel_epi64 (__m128i *__P, __m128i
*** 1619,1624 ****
--- 1638,1649 ----
*(long long *)__P = __builtin_ia32_movdq2q ((__v2di)__B);
}
+ static __inline __m64
+ _mm_movepi64_pi64 (__m128i __B)
+ {
+ return (__m64) __builtin_ia32_movdq2q ((__v2di)__B);
+ }
+
static __inline __m128i
_mm_move_epi64 (__m128i __A)
{
*************** _mm_add_epi32 (__m128i __A, __m128i __B)
*** 2048,2054 ****
static __inline __m128i
_mm_add_epi64 (__m128i __A, __m128i __B)
{
! return (__m128i)__builtin_ia32_paddq128 ((__v4si)__A, (__v4si)__B);
}
static __inline __m128i
--- 2116,2122 ----
static __inline __m128i
_mm_add_epi64 (__m128i __A, __m128i __B)
{
! return (__m128i)__builtin_ia32_paddq128 ((__v2di)__A, (__v2di)__B);
}
static __inline __m128i
*************** _mm_sub_epi32 (__m128i __A, __m128i __B)
*** 2096,2102 ****
static __inline __m128i
_mm_sub_epi64 (__m128i __A, __m128i __B)
{
! return (__m128i)__builtin_ia32_psubq128 ((__v4si)__A, (__v4si)__B);
}
static __inline __m128i
--- 2164,2170 ----
static __inline __m128i
_mm_sub_epi64 (__m128i __A, __m128i __B)
{
! return (__m128i)__builtin_ia32_psubq128 ((__v2di)__A, (__v2di)__B);
}
static __inline __m128i
*************** _mm_mullo_epi16 (__m128i __A, __m128i __
*** 2142,2148 ****
}
static __inline __m64
! _mm_mul_pu16 (__m64 __A, __m64 __B)
{
return (__m64)__builtin_ia32_pmuludq ((__v2si)__A, (__v2si)__B);
}
--- 2210,2216 ----
}
static __inline __m64
! _mm_mul_su32 (__m64 __A, __m64 __B)
{
return (__m64)__builtin_ia32_pmuludq ((__v2si)__A, (__v2si)__B);
}