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Power4 scheduling tweaks and SVR4 alignment macro
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 20 Feb 2003 11:26:19 -0500
- Subject: Power4 scheduling tweaks and SVR4 alignment macro
* config/rs6000/sysv4.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Define.
* config/rs6000/power4.md (power4-store,power4-vecstore): New
insn reservations.
(power4-fpstore): Compact.
Index: power4.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/power4.md,v
retrieving revision 1.2
diff -c -p -r1.2 power4.md
*** power4.md 15 Feb 2003 22:04:30 -0000 1.2
--- power4.md 20 Feb 2003 16:22:24 -0000
***************
*** 127,135 ****
"lsq_power4")
(define_insn_reservation "power4-store" 1
! (and (eq_attr "type" "store,vecstore")
(eq_attr "cpu" "power4"))
! "lsq_power4")
(define_insn_reservation "power4-store-update" 1
(and (eq_attr "type" "store_u")
--- 127,136 ----
"lsq_power4")
(define_insn_reservation "power4-store" 1
! (and (eq_attr "type" "store")
(eq_attr "cpu" "power4"))
! "((du1_power4|du4_power4),lsu1_power4,iu2_power4)\
! |((du2_power4|du3_power4),lsu2_power4,iu1_power4)")
(define_insn_reservation "power4-store-update" 1
(and (eq_attr "type" "store_u")
***************
*** 144,153 ****
(define_insn_reservation "power4-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4"))
! "(du1_power4,fpu1_power4,lsu1_power4)\
! |(du2_power4,fpu2_power4,lsu2_power4)\
! |(du3_power4,fpu2_power4,lsu2_power4)\
! |(du4_power4,fpu1_power4,lsu1_power4)")
(define_insn_reservation "power4-fpstore-update" 1
(and (eq_attr "type" "fpstore_u")
--- 145,152 ----
(define_insn_reservation "power4-fpstore" 1
(and (eq_attr "type" "fpstore")
(eq_attr "cpu" "power4"))
! "((du1_power4|du4_power4),lsu1_power4,fpu1_power4)\
! |((du2_power4|du3_power4),lsu2_power4,fpu2_power4)")
(define_insn_reservation "power4-fpstore-update" 1
(and (eq_attr "type" "fpstore_u")
***************
*** 162,167 ****
--- 161,172 ----
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4+du3_power4+du4_power4),
iu1_power4,fpu2_power4,(iu2_power4+lsu2_power4)")
+
+ (define_insn_reservation "power4-vecstore" 1
+ (and (eq_attr "type" "vecstore")
+ (eq_attr "cpu" "power4"))
+ "((du1_power4|du4_power4),lsu1_power4,vec_power4)\
+ |((du2_power4|du3_power4),lsu2_power4,vec_power4)")
; Integer latency is 2 cycles
Index: sysv4.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/sysv4.h,v
retrieving revision 1.115
diff -c -p -r1.115 sysv4.h
*** sysv4.h 13 Jan 2003 15:38:58 -0000 1.115
--- sysv4.h 20 Feb 2003 16:22:24 -0000
*************** do { \
*** 692,697 ****
--- 692,711 ----
ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
} while (0)
+ #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
+ /* To support -falign-* switches we need to use .p2align so
+ that alignment directives in code sections will be padded
+ with no-op instructions, rather than zeroes. */
+ #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
+ if ((LOG) != 0) \
+ { \
+ if ((MAX_SKIP) == 0) \
+ fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
+ else \
+ fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
+ }
+ #endif
+
/* This is how to output code to push a register on the stack.
It need not be very fast code.