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mips64-linux n32/n64 long doubles
- From: Alexandre Oliva <aoliva at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 26 Jan 2003 07:55:02 -0200
- Subject: mips64-linux n32/n64 long doubles
- Organization: GCC Team, Red Hat
These mips-specific bits still need review for the mips64-linux port
to be fully functional. It's an extract from the earlier irix6 long
double patch, from which I have removed all of the bits that have
already been checked and all irix6 bits that still need tweaking.
These changes are needed for both mips64-linux and irix6, but I put in
a temporary override in the irix configuration file, such that we keep
on using 64-bit long doubles until we're ready for the switch. Ok to
install?
Index: gcc/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* config/mips/mips.h (LONG_DUBLE_TYPE_SIZE): Set to 128 on N32
and N64.
(MAX_FIXED_MODE_SIZE): Define to LONG_DOUBLE_TYPE_SIZE.
(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Define.
(BIGGEST_ALIGNMENT): Same as LONG_DOUBLE_TYPE_SIZE.
(FUNCTION_VALUE_REGNO_P): Set for FP_RETURN+2 on N32 and N64.
* config/mips/mips.c (mips_arg_info): Pass TFmode values in
even FP registers on N32 and N64.
(mips_va_start): Adjust alignment of ARG_POINTER_REGNUM.
(mips_va_arg): Impose additional even-register-like alignment
to 128-bit arguments.
(override_options): Set TFmode format. Set it as allowable in
FP registers.
(mips_function_value): Return TFmode in $f0 and $f2 on N32 or
N64.
* config/mips/_tilib.c (__negti2, __ashlti3, __lshrti3): New.
* config/mips/iris6.h (LONG_DOUBLE_TYPE_SIZE): Override to 64.
(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Likewise.
Index: gcc/config/mips/_tilib.c
===================================================================
RCS file: gcc/config/mips/_tilib.c
diff -N gcc/config/mips/_tilib.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gcc/config/mips/_tilib.c 26 Jan 2003 08:10:29 -0000
@@ -0,0 +1,154 @@
+/* A few TImode functions needed for TFmode emulated arithmetic.
+ Copyright 2002, 2003 Free Software Foundation, Inc.
+ Contributed by Alexandre Oliva <aoliva@redhat.com>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+
+#include "tconfig.h"
+#include "tsystem.h"
+
+#ifndef LIBGCC2_WORDS_BIG_ENDIAN
+#define LIBGCC2_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN
+#endif
+
+#if _MIPS_SIM == 2 /* N32 */ || _MIPS_SIM == 3 /* 64 */
+
+typedef int TItype __attribute__ ((mode (TI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef int SItype __attribute__ ((mode (SI)));
+
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+
+typedef union
+{
+ struct TIstruct {
+#if LIBGCC2_WORDS_BIG_ENDIAN
+ DItype high, low;
+#else
+ DItype low, high;
+#endif
+ } s;
+ TItype ll;
+} TIunion;
+
+TItype
+__negti2 (TItype u)
+{
+ TIunion w;
+ TIunion uu;
+
+ uu.ll = u;
+
+ w.s.low = -uu.s.low;
+ w.s.high = -uu.s.high - ((UDItype) w.s.low > 0);
+
+ return w.ll;
+}
+
+TItype
+__ashlti3 (TItype u, int b)
+{
+ TIunion w;
+ int bm;
+ TIunion uu;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof (DItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0)
+ {
+ w.s.low = 0;
+ w.s.high = (UDItype) uu.s.low << -bm;
+ }
+ else
+ {
+ UDItype carries = (UDItype) uu.s.low >> bm;
+
+ w.s.low = (UDItype) uu.s.low << b;
+ w.s.high = ((UDItype) uu.s.high << b) | carries;
+ }
+
+ return w.ll;
+}
+
+#if 0
+TItype
+__ashrti3 (TItype u, int b)
+{
+ TIunion w;
+ int bm;
+ TIunion uu;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof (DItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0)
+ {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high = uu.s.high >> (sizeof (DItype) * BITS_PER_UNIT - 1);
+ w.s.low = uu.s.high >> -bm;
+ }
+ else
+ {
+ UDItype carries = (UDItype) uu.s.high << bm;
+
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((UDItype) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+#endif
+
+TItype
+__lshrti3 (TItype u, int b)
+{
+ TIunion w;
+ int bm;
+ TIunion uu;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof (DItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0)
+ {
+ w.s.high = 0;
+ w.s.low = (UDItype) uu.s.high >> -bm;
+ }
+ else
+ {
+ UDItype carries = (UDItype) uu.s.high << bm;
+
+ w.s.high = (UDItype) uu.s.high >> b;
+ w.s.low = ((UDItype) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
+
+#endif /* N32 or N64 */
Index: gcc/config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.247
diff -u -p -r1.247 mips.c
--- gcc/config/mips/mips.c 19 Jan 2003 13:04:24 -0000 1.247
+++ gcc/config/mips/mips.c 26 Jan 2003 08:10:35 -0000
@@ -4280,7 +4280,9 @@ mips_arg_info (cum, mode, type, named, i
info->fpr_p = false;
if (GET_MODE_CLASS (mode) == MODE_FLOAT
- && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
+ && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE * ((mips_abi == ABI_N32
+ || mips_abi == ABI_64)
+ ? 2 : 1))
{
switch (mips_abi)
{
@@ -4315,9 +4317,11 @@ mips_arg_info (cum, mode, type, named, i
is a double, but $f14 if it is a single. Otherwise, on a
32-bit double-float machine, each FP argument must start in a
new register pair. */
- even_reg_p = ((mips_abi == ABI_O64 && mode == SFmode) || FP_INC > 1);
+ even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_FPVALUE /* TFmode */
+ || (mips_abi == ABI_O64 && mode == SFmode)
+ || FP_INC > 1);
}
- else if (!TARGET_64BIT)
+ else if (!TARGET_64BIT || mips_abi == ABI_N32 || mips_abi == ABI_64)
{
if (GET_MODE_CLASS (mode) == MODE_INT
|| GET_MODE_CLASS (mode) == MODE_FLOAT)
@@ -4706,6 +4710,15 @@ mips_va_start (valist, nextarg)
{
const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
+ /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
+ since the stack is aligned for a pair of argument-passing slots,
+ and the beginning of a variable argument list may be an odd slot,
+ we have to decrease its alignment. */
+ if (cfun && cfun->emit->regno_pointer_align)
+ while (((current_function_pretend_args_size * BITS_PER_UNIT)
+ & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
+ REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
+
if (mips_abi == ABI_EABI)
{
int gpr_save_area_size;
@@ -4998,7 +5011,10 @@ mips_va_arg (valist, type)
that alignments <= UNITS_PER_WORD are preserved by the va_arg
increment mechanism. */
- if (TARGET_64BIT)
+ if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
+ && TYPE_ALIGN (type) > 64)
+ align = 16;
+ else if (TARGET_64BIT)
align = 8;
else if (TYPE_ALIGN (type) > 32)
align = 8;
@@ -5452,7 +5468,10 @@ override_options ()
register. */
|| (mips_abi == ABI_MEABI && size <= 4))
&& (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
- && size <= UNITS_PER_FPVALUE)
+ && size <= (UNITS_PER_FPVALUE
+ * ((mips_abi == ABI_N32
+ || mips_abi == ABI_64)
+ ? 2 : 1)))
/* Allow integer modes that fit into a single
register. We need to put integers into FPRs
when using instructions like cvt and trunc. */
@@ -8264,8 +8283,24 @@ mips_function_value (valtype, func, mode
}
mclass = GET_MODE_CLASS (mode);
- if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
+ if (mclass == MODE_FLOAT
+ && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
reg = FP_RETURN;
+
+ else if (mclass == MODE_FLOAT
+ && mode == TFmode
+ && (mips_abi == ABI_N32 || mips_abi == ABI_64))
+ /* long doubles are really split between f0 and f2, not f1. Eek. */
+ return gen_rtx_PARALLEL
+ (VOIDmode,
+ gen_rtvec (2,
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (DImode, FP_RETURN),
+ GEN_INT (0)),
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (DImode, FP_RETURN + 2),
+ GEN_INT (GET_MODE_SIZE (mode) / 2))));
+
else if (mclass == MODE_COMPLEX_FLOAT
&& GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE * 2)
Index: gcc/config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.234
diff -u -p -r1.234 mips.h
--- gcc/config/mips/mips.h 19 Jan 2003 13:04:24 -0000 1.234
+++ gcc/config/mips/mips.h 26 Jan 2003 08:10:39 -0000
@@ -1565,7 +1565,21 @@ do { \
/* A C expression for the size in bits of the type `long double' on
the target machine. If you don't define this, the default is two
words. */
-#define LONG_DOUBLE_TYPE_SIZE 64
+#define LONG_DOUBLE_TYPE_SIZE \
+ (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
+
+/* long double is not a fixed mode, but the idea is that, if we
+ support long double, we also want a 128-bit integer type. */
+#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
+
+#ifdef IN_LIBGCC2
+#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
+ || (defined _ABI64 && _MIPS_SIM == _ABI64)
+# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
+# else
+# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
+# endif
+#endif
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
@@ -1592,7 +1606,8 @@ do { \
#define STRUCTURE_SIZE_BOUNDARY 8
/* There is no point aligning anything to a rounder boundary than this. */
-#define BIGGEST_ALIGNMENT 64
+#define BIGGEST_ALIGNMENT ((mips_abi == ABI_N32 || mips_abi == ABI_64) \
+ ? 128 : 64)
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
@@ -2654,7 +2669,9 @@ extern enum reg_class mips_char_to_class
On the MIPS, R2 R3 and F0 F2 are the only register thus used.
Currently, R2 and F0 are only implemented here (C has no complex type) */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
+ || ((mips_abi == ABI_N32 || mips_abi == ABI_64) && FP_RETURN != GP_RETURN \
+ && (N) == FP_RETURN + 2))
/* 1 if N is a possible register number for function argument passing.
We have no FP argument registers when soft-float. When FP registers
Index: gcc/config/mips/iris6.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/iris6.h,v
retrieving revision 1.55
diff -u -p -r1.55 iris6.h
--- gcc/config/mips/iris6.h 19 Jan 2003 13:04:23 -0000 1.55
+++ gcc/config/mips/iris6.h 26 Jan 2003 08:27:51 -0000
@@ -511,3 +511,9 @@ do { \
%{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64}%{!mabi*: -n32}"
#define MIPS_TFMODE_FORMAT ibm_extended_format
+
+/* We're not ready to switch to 128-bit long doubles yet. */
+#undef LONG_DOUBLE_TYPE_SIZE
+#define LONG_DOUBLE_TYPE_SIZE 64
+#undef LIBGCC2_LONG_DOUBLE_TYPE_SIZE
+#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer