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PATCH ARM: Clean out dead XFmode support
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard dot Earnshaw at arm dot com
- Date: Wed, 08 Jan 2003 12:00:57 +0000
- Subject: PATCH ARM: Clean out dead XFmode support
- Organization: ARM Ltd.
- Reply-to: Richard dot Earnshaw at arm dot com
This patch cleans up the code that was added a long time ago to support
XFmode instructions on the FPA, but was never enabled for various reasons.
It also deletes a few patterns that have been commented out for a long
while, because it was better to use library routines than the
always-emulated FPA instructions.
built on arm-elf (and tested on a FPA emulation).
2003-01-08 Richard Earnshaw <rearnsha@arm.com>
* arm.h (ENABLE_XF_PATTERNS): Delete.
* arm.md (addxf3, subxf3, mulxf3, divxf3, modxf3, negxf2, absxf2)
(sqrtxf2, floatsixf2, fix_truncxfsi2, truncxfsf2, truncxfdf2)
(extendsfxf2, extenddfxf2, movxf, cmpxf, cmpxf_insn)
(cmpxf_trap): Delete.
(movxf_hard_insn): Remove test of ENABLE_XF_PATTERNS.
Index: arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.170
diff -p -r1.170 arm.h
*** arm.h 1 Jan 2003 12:26:55 -0000 1.170
--- arm.h 8 Jan 2003 11:40:31 -0000
*************** extern int arm_is_6_or_7;
*** 641,660 ****
/* This is required to ensure that push insns always push a word. */
#define PROMOTE_FUNCTION_ARGS
- /* For the ARM:
- I think I have added all the code to make this work. Unfortunately,
- early releases of the floating point emulation code on RISCiX used a
- different format for extended precision numbers. On my RISCiX box there
- is a bug somewhere which causes the machine to lock up when running enquire
- with long doubles. There is the additional aspect that Norcroft C
- treats long doubles as doubles and we ought to remain compatible.
- Perhaps someone with an FPA coprocessor and not running RISCiX would like
- to try this someday. */
- /* #define LONG_DOUBLE_TYPE_SIZE 96 */
-
- /* Disable XFmode patterns in md file */
- #define ENABLE_XF_PATTERNS 0
-
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 0
--- 641,646 ----
Index: arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.114
diff -p -r1.114 arm.md
*** arm.md 16 Dec 2002 18:20:56 -0000 1.114
--- arm.md 8 Jan 2003 11:40:32 -0000
***************
*** 24,32 ****
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
- ;; There are patterns in this file to support XFmode arithmetic.
- ;; Unfortunately RISC iX doesn't work well with these so they are disabled.
- ;; (See arm.h)
;;---------------------------------------------------------------------------
;; Constants
--- 24,29 ----
***************
*** 153,159 ****
; mult a multiply instruction
; block blockage insn, this blocks all functional units
; float a floating point arithmetic operation (subject to expansion)
- ; fdivx XFmode floating point division
; fdivd DFmode floating point division
; fdivs SFmode floating point division
; fmul Floating point multiply
--- 150,155 ----
***************
*** 856,873 ****
(set_attr "predicable" "yes")]
)
- (define_insn "addxf3"
- [(set (match_operand:XF 0 "s_register_operand" "=f,f")
- (plus:XF (match_operand:XF 1 "s_register_operand" "f,f")
- (match_operand:XF 2 "fpu_add_operand" "fG,H")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "@
- adf%?e\\t%0, %1, %2
- suf%?e\\t%0, %1, #%N2"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
- )
-
(define_expand "subdi3"
[(parallel
[(set (match_operand:DI 0 "s_register_operand" "")
--- 852,857 ----
***************
*** 1119,1136 ****
[(set_attr "type" "farith")
(set_attr "predicable" "yes")]
)
-
- (define_insn "subxf3"
- [(set (match_operand:XF 0 "s_register_operand" "=f,f")
- (minus:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G")
- (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "@
- suf%?e\\t%0, %1, %2
- rsf%?e\\t%0, %2, %1"
- [(set_attr "type" "farith")
- (set_attr "predicable" "yes")]
- )
;; Multiplication insns
--- 1103,1108 ----
***************
*** 1415,1430 ****
[(set_attr "type" "fmul")
(set_attr "predicable" "yes")]
)
-
- (define_insn "mulxf3"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (mult:XF (match_operand:XF 1 "s_register_operand" "f")
- (match_operand:XF 2 "fpu_rhs_operand" "fG")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "muf%?e\\t%0, %1, %2"
- [(set_attr "type" "fmul")
- (set_attr "predicable" "yes")]
- )
;; Division insns
--- 1387,1392 ----
***************
*** 1485,1502 ****
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
-
- (define_insn "divxf3"
- [(set (match_operand:XF 0 "s_register_operand" "=f,f")
- (div:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G")
- (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "@
- dvf%?e\\t%0, %1, %2
- rdf%?e\\t%0, %2, %1"
- [(set_attr "type" "fdivx")
- (set_attr "predicable" "yes")]
- )
;; Modulo insns
--- 1447,1452 ----
***************
*** 1553,1568 ****
[(set_attr "type" "fdivd")
(set_attr "predicable" "yes")]
)
-
- (define_insn "modxf3"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (mod:XF (match_operand:XF 1 "s_register_operand" "f")
- (match_operand:XF 2 "fpu_rhs_operand" "fG")))]
- "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "rmf%?e\\t%0, %1, %2"
- [(set_attr "type" "fdivx")
- (set_attr "predicable" "yes")]
- )
;; Boolean and,ior,xor insns
--- 1503,1508 ----
***************
*** 2793,2807 ****
(set_attr "predicable" "yes")]
)
- (define_insn "negxf2"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (neg:XF (match_operand:XF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "mnf%?e\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
- )
-
;; abssi2 doesn't really clobber the condition codes if a different register
;; is being set. To keep things simple, assume during rtl manipulations that
;; it does, but tell the final scan operator the truth. Similarly for
--- 2733,2738 ----
***************
*** 2863,2877 ****
(set_attr "predicable" "yes")]
)
- (define_insn "absxf2"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (abs:XF (match_operand:XF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "abs%?e\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
- )
-
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))]
--- 2794,2799 ----
***************
*** 2900,2982 ****
(set_attr "predicable" "yes")]
)
- (define_insn "sqrtxf2"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (sqrt:XF (match_operand:XF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "sqt%?e\\t%0, %1"
- [(set_attr "type" "float_em")
- (set_attr "predicable" "yes")]
- )
-
- ;; SIN COS TAN and family are always emulated, so it's probably better
- ;; to always call a library function.
- ;(define_insn "sinsf2"
- ; [(set (match_operand:SF 0 "s_register_operand" "=f")
- ; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")]
- ; UNSPEC_SIN))]
- ; "TARGET_ARM && TARGET_HARD_FLOAT"
- ; "sin%?s\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "sindf2"
- ; [(set (match_operand:DF 0 "s_register_operand" "=f")
- ; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")]
- ; UNSPEC_SIN))]
- ; "TARGET_ARM && TARGET_HARD_FLOAT"
- ; "sin%?d\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "*sindf_esfdf"
- ; [(set (match_operand:DF 0 "s_register_operand" "=f")
- ; (unspec:DF [(float_extend:DF
- ; (match_operand:SF 1 "s_register_operand" "f"))]
- ; UNSPEC_SIN))]
- ; "TARGET_ARM && TARGET_HARD_FLOAT"
- ; "sin%?d\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "sinxf2"
- ; [(set (match_operand:XF 0 "s_register_operand" "=f")
- ; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")]
- ; UNSPEC_SIN))]
- ; "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- ; "sin%?e\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "cossf2"
- ; [(set (match_operand:SF 0 "s_register_operand" "=f")
- ; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")]
- ; UNSPEC_COS))]
- ; "TARGET_ARM && TARGET_HARD_FLOAT"
- ; "cos%?s\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "cosdf2"
- ; [(set (match_operand:DF 0 "s_register_operand" "=f")
- ; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")]
- ; UNSPEC_COS))]
- ; "TARGET_ARM && TARGET_HARD_FLOAT"
- ; "cos%?d\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "*cosdf_esfdf"
- ; [(set (match_operand:DF 0 "s_register_operand" "=f")
- ; (unspec:DF [(float_extend:DF
- ; (match_operand:SF 1 "s_register_operand" "f"))]
- ; UNSPEC_COS))]
- ; "TARGET_ARM && TARGET_HARD_FLOAT"
- ; "cos%?d\\t%0, %1"
- ;[(set_attr "type" "float_em")])
- ;
- ;(define_insn "cosxf2"
- ; [(set (match_operand:XF 0 "s_register_operand" "=f")
- ; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")]
- ; UNSEPC_COS))]
- ; "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- ; "cos%?e\\t%0, %1"
- ;[(set_attr "type" "float_em")])
-
(define_insn_and_split "one_cmpldi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
(not:DI (match_operand:DI 1 "s_register_operand" "?r,0")))]
--- 2822,2827 ----
***************
*** 3060,3074 ****
(set_attr "predicable" "yes")]
)
- (define_insn "floatsixf2"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (float:XF (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "flt%?e\\t%0, %1"
- [(set_attr "type" "r_2_f")
- (set_attr "predicable" "yes")]
- )
-
(define_insn "fix_truncsfsi2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(fix:SI (match_operand:SF 1 "s_register_operand" "f")))]
--- 2905,2910 ----
***************
*** 3087,3101 ****
(set_attr "predicable" "yes")]
)
- (define_insn "fix_truncxfsi2"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (match_operand:XF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "fix%?z\\t%0, %1"
- [(set_attr "type" "f_2_r")
- (set_attr "predicable" "yes")]
- )
-
;; Truncation insns
(define_insn "truncdfsf2"
--- 2923,2928 ----
***************
*** 3107,3132 ****
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
-
- (define_insn "truncxfsf2"
- [(set (match_operand:SF 0 "s_register_operand" "=f")
- (float_truncate:SF
- (match_operand:XF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "mvf%?s\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
- )
-
- (define_insn "truncxfdf2"
- [(set (match_operand:DF 0 "s_register_operand" "=f")
- (float_truncate:DF
- (match_operand:XF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "mvf%?d\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
- )
;; Zero and sign extension instructions.
--- 2934,2939 ----
***************
*** 3858,3882 ****
[(set_attr "type" "ffarith")
(set_attr "predicable" "yes")]
)
-
- (define_insn "extendsfxf2"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (float_extend:XF (match_operand:SF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "mvf%?e\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
- )
-
- (define_insn "extenddfxf2"
- [(set (match_operand:XF 0 "s_register_operand" "=f")
- (float_extend:XF (match_operand:DF 1 "s_register_operand" "f")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "mvf%?e\\t%0, %1"
- [(set_attr "type" "ffarith")
- (set_attr "predicable" "yes")]
- )
-
;; Move insns (including loads and stores)
--- 3665,3670 ----
***************
*** 5173,5191 ****
)
! (define_expand "movxf"
! [(set (match_operand:XF 0 "general_operand" "")
! (match_operand:XF 1 "general_operand" ""))]
! "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
! "")
!
! ;; Even when the XFmode patterns aren't enabled, we enable this after
! ;; reloading so that we can push floating point registers in the prologue.
(define_insn "*movxf_hard_insn"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r")
(match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
! "TARGET_ARM && TARGET_HARD_FLOAT && (ENABLE_XF_PATTERNS || reload_completed)"
"*
switch (which_alternative)
{
--- 4961,4975 ----
)
! ;; Saving and restoring the floating point registers in the prologue should
! ;; be done in XFmode, even though we don't support that for anything else
! ;; (Well, strictly it's 'internal representation', but that's effectively
! ;; XFmode).
(define_insn "*movxf_hard_insn"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r")
(match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))]
! "TARGET_ARM && TARGET_HARD_FLOAT && reload_completed"
"*
switch (which_alternative)
{
***************
*** 5652,5668 ****
"
)
- (define_expand "cmpxf"
- [(match_operand:XF 0 "s_register_operand" "")
- (match_operand:XF 1 "fpu_rhs_operand" "")]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "
- arm_compare_op0 = operands[0];
- arm_compare_op1 = operands[1];
- DONE;
- "
- )
-
(define_insn "*arm_cmpsi_insn"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
--- 5436,5441 ----
***************
*** 5761,5778 ****
(set_attr "type" "f_2_r")]
)
- (define_insn "*cmpxf_insn"
- [(set (reg:CCFP CC_REGNUM)
- (compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f")
- (match_operand:XF 1 "fpu_add_operand" "fG,H")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "@
- cmf%?\\t%0, %1
- cnf%?\\t%0, #%N1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
- )
-
(define_insn "*cmpsf_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
--- 5534,5539 ----
***************
*** 5817,5834 ****
(match_operand:SF 1 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"cmf%?e\\t%0, %1"
- [(set_attr "conds" "set")
- (set_attr "type" "f_2_r")]
- )
-
- (define_insn "*cmpxf_trap"
- [(set (reg:CCFPE CC_REGNUM)
- (compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f")
- (match_operand:XF 1 "fpu_add_operand" "fG,H")))]
- "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT"
- "@
- cmf%?e\\t%0, %1
- cnf%?e\\t%0, #%N1"
[(set_attr "conds" "set")
(set_attr "type" "f_2_r")]
)
--- 5578,5583 ----