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patches applied to sh port
- From: Joern Rennecke <joern dot rennecke at superh dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 11 Dec 2002 20:03:02 +0000
- Subject: patches applied to sh port
- Organization: SuperH UK Ltd.
--
--------------------------
SuperH (UK) Ltd.
2410 Aztec West / Almondsbury / BRISTOL / BS32 4QX
T:+44 1454 465658
Wed Dec 11 18:39:52 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh.h (REG_CLASS_HAS_GENERAL_REG): New.
(REGISTER_MOVE_COST): Use it.
Index: config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.175
diff -p -r1.175 sh.h
*** config/sh/sh.h 6 Dec 2002 15:49:49 -0000 1.175
--- config/sh/sh.h 11 Dec 2002 18:39:46 -0000
*************** while (0)
*** 2811,2830 ****
If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
it uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
(((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
: ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
|| (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
! && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
! || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
&& ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
|| (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
? (TARGET_SHMEDIA ? 4 \
: TARGET_FMOVD ? 8 : 12) \
: (((DSTCLASS) == FPUL_REGS \
! && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
! || (SRCCLASS == FPUL_REGS \
! && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
? 5 \
: (((DSTCLASS) == FPUL_REGS \
&& ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
--- 2811,2835 ----
If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
it uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */
+
+ #define REGCLASS_HAS_GENERAL_REG(rclass) \
+ ((rclass)==GENERAL_REGS||(rclass)==R0_REGS||(rclass)==SIBCALL_REGS)
+ /* NB SIBCALL_REGS are not strictly general, as they include TR0-TR4 */
+
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
(((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
: ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
|| (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
! && REGCLASS_HAS_GENERAL_REG (SRCCLASS)) \
! || (REGCLASS_HAS_GENERAL_REG (DSTCLASS) \
&& ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
|| (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
? (TARGET_SHMEDIA ? 4 \
: TARGET_FMOVD ? 8 : 12) \
: (((DSTCLASS) == FPUL_REGS \
! && REGCLASS_HAS_GENERAL_REG (SRCCLASS)) \
! || ((SRCCLASS) == FPUL_REGS \
! && REGCLASS_HAS_GENERAL_REG (DSTCLASS))) \
? 5 \
: (((DSTCLASS) == FPUL_REGS \
&& ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
*************** while (0)
*** 2832,2842 ****
|| ((SRCCLASS) == FPUL_REGS \
&& ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
? 7 \
! : (((SRCCLASS) == TARGET_REGS && (DSTCLASS) != GENERAL_REGS) \
! || ((DSTCLASS) == TARGET_REGS && (SRCCLASS) != GENERAL_REGS)) \
? 20 \
! : (((SRCCLASS) == FPSCR_REGS && (DSTCLASS) != GENERAL_REGS) \
! || ((DSTCLASS) == FPSCR_REGS && (SRCCLASS) != GENERAL_REGS)) \
? 4 \
: 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
--- 2837,2851 ----
|| ((SRCCLASS) == FPUL_REGS \
&& ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
? 7 \
! : (((SRCCLASS) == TARGET_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (DSTCLASS)) \
! || ((DSTCLASS) == TARGET_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (SRCCLASS))) \
? 20 \
! : (((SRCCLASS) == FPSCR_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (DSTCLASS)) \
! || ((DSTCLASS) == FPSCR_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (SRCCLASS))) \
? 4 \
: 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
Wed Dec 11 19:05:05 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh.h (REG_CLASS_HAS_FP_REG): New.
(REGISTER_MOVE_COST) Use it. Put body into a function and
move it into:
* sh.c (sh_register_move_cost).
* sh-protos.h (sh_register_move_cost): Declare.
* sh.c (sh_expand_builtin): Abort for unexpected nop values.
(sh_adjust_cost): Always return a value.
Index: config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.176
diff -p -r1.176 sh.h
*** config/sh/sh.h 11 Dec 2002 18:42:11 -0000 1.176
--- config/sh/sh.h 11 Dec 2002 20:01:43 -0000
*************** while (0)
*** 2812,2853 ****
it uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */
! #define REGCLASS_HAS_GENERAL_REG(rclass) \
! ((rclass)==GENERAL_REGS||(rclass)==R0_REGS||(rclass)==SIBCALL_REGS)
/* NB SIBCALL_REGS are not strictly general, as they include TR0-TR4 */
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
! (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
! : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
! || (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
! && REGCLASS_HAS_GENERAL_REG (SRCCLASS)) \
! || (REGCLASS_HAS_GENERAL_REG (DSTCLASS) \
! && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
! || (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
! ? (TARGET_SHMEDIA ? 4 \
! : TARGET_FMOVD ? 8 : 12) \
! : (((DSTCLASS) == FPUL_REGS \
! && REGCLASS_HAS_GENERAL_REG (SRCCLASS)) \
! || ((SRCCLASS) == FPUL_REGS \
! && REGCLASS_HAS_GENERAL_REG (DSTCLASS))) \
! ? 5 \
! : (((DSTCLASS) == FPUL_REGS \
! && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
! || (SRCCLASS) == T_REGS)) \
! || ((SRCCLASS) == FPUL_REGS \
! && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
! ? 7 \
! : (((SRCCLASS) == TARGET_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (DSTCLASS)) \
! || ((DSTCLASS) == TARGET_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (SRCCLASS))) \
! ? 20 \
! : (((SRCCLASS) == FPSCR_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (DSTCLASS)) \
! || ((DSTCLASS) == FPSCR_REGS \
! && ! REGCLASS_HAS_GENERAL_REG (SRCCLASS))) \
! ? 4 \
! : 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
would be so that people with slow memory systems could generate
--- 2812,2827 ----
it uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */
! #define REGCLASS_HAS_GENERAL_REG(CLASS) \
! ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == SIBCALL_REGS)
/* NB SIBCALL_REGS are not strictly general, as they include TR0-TR4 */
+ #define REGCLASS_HAS_FP_REG(CLASS) \
+ ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
+ || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
+
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
! sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
would be so that people with slow memory systems could generate
Index: config/sh/sh.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.c,v
retrieving revision 1.185
diff -p -r1.185 sh.c
*** config/sh/sh.c 6 Dec 2002 20:10:50 -0000 1.185
--- config/sh/sh.c 11 Dec 2002 20:01:43 -0000
*************** sh_hard_regno_rename_ok (old_reg, new_re
*** 7008,7019 ****
return 1;
}
! /* A C statement (sans semicolon) to update the integer variable COST
based on the relationship between INSN that is dependent on
DEP_INSN through the dependence LINK. The default is to make no
adjustment to COST. This can be used for example to specify to
the scheduler that an output- or anti-dependence does not incur
! the same cost as a data-dependence. */
static int
sh_adjust_cost (insn, link, dep_insn, cost)
rtx insn;
--- 7008,7020 ----
return 1;
}
! /* Function to update the integer COST
based on the relationship between INSN that is dependent on
DEP_INSN through the dependence LINK. The default is to make no
adjustment to COST. This can be used for example to specify to
the scheduler that an output- or anti-dependence does not incur
! the same cost as a data-dependence. The return value should be
! the new value for COST. */
static int
sh_adjust_cost (insn, link, dep_insn, cost)
rtx insn;
*************** sh_adjust_cost (insn, link, dep_insn, co
*** 7040,7046 ****
if (recog_memoized (insn) < 0
|| recog_memoized (dep_insn) < 0)
! return;
dep_type = get_attr_type (dep_insn);
if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
--- 7041,7047 ----
if (recog_memoized (insn) < 0
|| recog_memoized (dep_insn) < 0)
! return cost;
dep_type = get_attr_type (dep_insn);
if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
*************** sh_expand_builtin (exp, target, subtarge
*** 7699,7704 ****
--- 7700,7707 ----
case 4:
pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
break;
+ default:
+ abort ();
}
if (! pat)
return 0;
*************** sh_mark_label (address, nuses)
*** 7776,7781 ****
--- 7779,7830 ----
if (GET_CODE (address) == LABEL_REF
&& GET_CODE (XEXP (address, 0)) == CODE_LABEL)
LABEL_NUSES (XEXP (address, 0)) += nuses;
+ }
+
+ /* Compute extra cost of moving data between one register class
+ and another. */
+
+ /* Regclass always uses 2 for moves in the same register class;
+ If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
+ it uses this information. Hence, the general register <-> floating point
+ register information here is not used for SFmode. */
+
+ int
+ sh_register_move_cost (mode, srcclass, dstclass)
+ enum machine_mode mode;
+ enum reg_class srcclass, dstclass;
+ {
+ if (dstclass == T_REGS || dstclass == PR_REGS)
+ return 10;
+
+ if ((REGCLASS_HAS_FP_REG (dstclass)
+ && REGCLASS_HAS_GENERAL_REG (srcclass))
+ || (REGCLASS_HAS_GENERAL_REG (dstclass)
+ && REGCLASS_HAS_FP_REG (srcclass)))
+ return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
+ * ((GET_MODE_SIZE (mode) + 7) / 8U));
+
+ if ((dstclass == FPUL_REGS
+ && REGCLASS_HAS_GENERAL_REG (srcclass))
+ || (srcclass == FPUL_REGS
+ && REGCLASS_HAS_GENERAL_REG (dstclass)))
+ return 5;
+
+ if ((dstclass == FPUL_REGS
+ && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
+ || (srcclass == FPUL_REGS
+ && (dstclass == PR_REGS || dstclass == MAC_REGS)))
+ return 7;
+
+ if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
+ || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
+ return 20;
+
+ if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
+ || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
+ return 4;
+
+ return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
}
#include "gt-sh.h"
Index: config/sh/sh-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh-protos.h,v
retrieving revision 1.33
diff -p -r1.33 sh-protos.h
*** config/sh/sh-protos.h 18 Nov 2002 14:01:23 -0000 1.33
--- config/sh/sh-protos.h 11 Dec 2002 20:01:43 -0000
*************** extern void sh_initialize_trampoline PAR
*** 129,134 ****
--- 129,136 ----
extern enum reg_class sh_cannot_change_mode_class
PARAMS ((enum machine_mode, enum machine_mode));
extern void sh_mark_label PARAMS ((rtx, int));
+ extern int sh_register_move_cost
+ PARAMS ((enum machine_mode mode, enum reg_class, enum reg_class));
#ifdef HARD_CONST
extern void fpscr_set_from_mem PARAMS ((int, HARD_REG_SET));