This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[patch] h8300.md: Add one define_insn_and_split.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 29 Nov 2002 11:10:27 -0500 (EST)
- Subject: [patch] h8300.md: Add one define_insn_and_split.
Hi,
Attached is a patch to add a define_insn_and_split pattern.
Without the patch, the bit test insns are not generated for things
like p[1] & 0x40, where p is a pointer to unsigned char *. The reason
is that the H8 bit test insn does not accept an address with an
offset.
The patch adds an insn to accept such address and then later split
that into a load and a bit test.
Tested on h8300 port. Committed.
Kazu Hirata
2002-11-29 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.md (an anonymous pattern): Give an
internal name *tst_extzv_bitqi_1_n.
Accept bit_operand instead of bit_memory_operand.
Do not accept bit tests with the MSB.
(*tst_extzv_memqi_1_n): New.
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.111
diff -c -r1.111 h8300.md
*** h8300.md 28 Nov 2002 18:02:46 -0000 1.111
--- h8300.md 29 Nov 2002 15:53:54 -0000
***************
*** 580,593 ****
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
! (define_insn ""
! [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
(match_operand 1 "const_int_operand" "n,n")))]
! "TARGET_H8300H || TARGET_H8300S"
"btst %Z1,%Y0"
[(set_attr "length" "2,8")
(set_attr "cc" "set_zn,set_zn")])
(define_insn ""
[(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
--- 580,611 ----
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
! (define_insn "*tst_extzv_bitqi_1_n"
! [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_operand" "r,U")
(const_int 1)
(match_operand 1 "const_int_operand" "n,n")))]
! "(TARGET_H8300H || TARGET_H8300S)
! && INTVAL (operands[1]) != 7"
"btst %Z1,%Y0"
[(set_attr "length" "2,8")
(set_attr "cc" "set_zn,set_zn")])
+
+ (define_insn_and_split "*tst_extzv_memqi_1_n"
+ [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
+ (const_int 1)
+ (match_operand 1 "const_int_operand" "n")))
+ (clobber (match_scratch:QI 2 "=&r"))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && !EXTRA_CONSTRAINT (operands[0], 'U')
+ && INTVAL (operands[1]) != 7"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (match_dup 0))
+ (set (cc0) (zero_extract:SI (match_dup 2)
+ (const_int 1)
+ (match_dup 1)))]
+ "")
(define_insn ""
[(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")