This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[e500] removing instructions

Motorola has decided not to include the following insructions in the
e500.  I've removed the builtins, patterns, and enum's.

Committed to mainline.

Aldy

2002-11-25  Aldy Hernandez  <aldyh@redhat.com>

	* config/rs6000/rs6000.h (enum rs6000_builtins): Remove evmwlssf,
	evmwlsmf, evmwlssfa, evmwlsmfa, evmwlssfaaw, evmwlsmfaaw,
	evmwlssfanw, evmwlsmfanw.

	* config/rs6000/rs6000.c (bdesc_2arg): Same.

	* config/rs6000/spe.md: Same for patterns.

Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.234
diff -c -p -r1.234 rs6000.h
*** config/rs6000/rs6000.h	4 Nov 2002 16:57:09 -0000	1.234
--- config/rs6000/rs6000.h	25 Nov 2002 19:31:57 -0000
*************** enum rs6000_builtins
*** 3182,3197 ****
    SPE_BUILTIN_EVMWHSSFA,
    SPE_BUILTIN_EVMWHUMI,
    SPE_BUILTIN_EVMWHUMIA,
-   SPE_BUILTIN_EVMWLSMF,
-   SPE_BUILTIN_EVMWLSMFA,
-   SPE_BUILTIN_EVMWLSMFAAW,
-   SPE_BUILTIN_EVMWLSMFANW,
    SPE_BUILTIN_EVMWLSMIAAW,
    SPE_BUILTIN_EVMWLSMIANW,
-   SPE_BUILTIN_EVMWLSSF,
-   SPE_BUILTIN_EVMWLSSFA,
-   SPE_BUILTIN_EVMWLSSFAAW,
-   SPE_BUILTIN_EVMWLSSFANW,
    SPE_BUILTIN_EVMWLSSIAAW,
    SPE_BUILTIN_EVMWLSSIANW,
    SPE_BUILTIN_EVMWLUMI,
--- 3182,3189 ----
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.399
diff -c -p -r1.399 rs6000.c
*** config/rs6000/rs6000.c	22 Nov 2002 02:22:13 -0000	1.399
--- config/rs6000/rs6000.c	25 Nov 2002 19:32:05 -0000
*************** static struct builtin_description bdesc_
*** 3928,3943 ****
    { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
    { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
    { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
-   { 0, CODE_FOR_spe_evmwlsmf, "__builtin_spe_evmwlsmf", SPE_BUILTIN_EVMWLSMF },
-   { 0, CODE_FOR_spe_evmwlsmfa, "__builtin_spe_evmwlsmfa", SPE_BUILTIN_EVMWLSMFA },
-   { 0, CODE_FOR_spe_evmwlsmfaaw, "__builtin_spe_evmwlsmfaaw", SPE_BUILTIN_EVMWLSMFAAW },
-   { 0, CODE_FOR_spe_evmwlsmfanw, "__builtin_spe_evmwlsmfanw", SPE_BUILTIN_EVMWLSMFANW },
    { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
    { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
-   { 0, CODE_FOR_spe_evmwlssf, "__builtin_spe_evmwlssf", SPE_BUILTIN_EVMWLSSF },
-   { 0, CODE_FOR_spe_evmwlssfa, "__builtin_spe_evmwlssfa", SPE_BUILTIN_EVMWLSSFA },
-   { 0, CODE_FOR_spe_evmwlssfaaw, "__builtin_spe_evmwlssfaaw", SPE_BUILTIN_EVMWLSSFAAW },
-   { 0, CODE_FOR_spe_evmwlssfanw, "__builtin_spe_evmwlssfanw", SPE_BUILTIN_EVMWLSSFANW },
    { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
    { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
    { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
--- 3928,3935 ----
Index: config/rs6000/spe.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/spe.md,v
retrieving revision 1.4
diff -c -p -r1.4 spe.md
*** config/rs6000/spe.md	1 Oct 2002 20:39:03 -0000	1.4
--- config/rs6000/spe.md	25 Nov 2002 19:32:05 -0000
***************
*** 1540,1586 ****
    [(set_attr "type" "veccomplex")
     (set_attr  "length" "4")])
  
- (define_insn "spe_evmwlsmfaaw"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")
- 		      (reg:V2SI SPE_ACC_REGNO)] 631))
-    (clobber (reg:V2SI SPE_ACC_REGNO))]
-   "TARGET_SPE"
-   "evmwlsmfaaw %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlsmfanw"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")
- 		      (reg:V2SI SPE_ACC_REGNO)] 632))
-    (clobber (reg:V2SI SPE_ACC_REGNO))]
-   "TARGET_SPE"
-   "evmwlsmfanw %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlsmfa"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")] 633))
-    (clobber (reg:V2SI SPE_ACC_REGNO))]
-   "TARGET_SPE"
-   "evmwlsmfa %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlsmf"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")] 634))]
-   "TARGET_SPE"
-   "evmwlsmf %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
  (define_insn "spe_evmwlsmiaaw"
    [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
          (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
--- 1540,1545 ----
***************
*** 1600,1650 ****
     (clobber (reg:V2SI SPE_ACC_REGNO))]
    "TARGET_SPE"
    "evmwlsmianw %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlssf"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")] 637))
-    (clobber (reg:SI SPEFSCR_REGNO))]
-   "TARGET_SPE"
-   "evmwlssf %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlssfa"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")] 638))
-    (clobber (reg:SI SPEFSCR_REGNO))
-    (clobber (reg:V2SI SPE_ACC_REGNO))]
-   "TARGET_SPE"
-   "evmwlssfa %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlssfaaw"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")
- 		      (reg:V2SI SPE_ACC_REGNO)] 639))
-    (clobber (reg:SI SPEFSCR_REGNO))
-    (clobber (reg:V2SI SPE_ACC_REGNO))]
-   "TARGET_SPE"
-   "evmwlssfaaw %0,%1,%2"
-   [(set_attr "type" "veccomplex")
-    (set_attr  "length" "4")])
- 
- (define_insn "spe_evmwlssfanw"
-   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
-         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
-                       (match_operand:V2SI 2 "gpc_reg_operand" "r")
- 		      (reg:V2SI SPE_ACC_REGNO)] 640))
-    (clobber (reg:SI SPEFSCR_REGNO))
-    (clobber (reg:V2SI SPE_ACC_REGNO))]
-   "TARGET_SPE"
-   "evmwlssfanw %0,%1,%2"
    [(set_attr "type" "veccomplex")
     (set_attr  "length" "4")])
  
--- 1559,1564 ----
Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]