Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.222
diff -u -d -b -w -u -b -B -d -p -r1.222 rs6000.md
--- config/rs6000/rs6000.md	16 Nov 2002 18:01:51 -0000	1.222
+++ config/rs6000/rs6000.md	19 Nov 2002 00:46:25 -0000
@@ -5239,6 +5239,7 @@
   "{fd|fdiv} %0,%1,%2"
   [(set_attr "type" "ddiv")])
 
+;; fmadd: D = (A * B) + C
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
@@ -5257,6 +5258,7 @@
   "{fma|fmadd} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fmsub 1: D = (A * B) - C
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
@@ -5275,6 +5277,69 @@
   "{fms|fmsub} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fmsub 2: D = -C + (A * B)
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+		 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fmsubs %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+		 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fms|fmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fmsub 3: D = - ((-A * B) + C)
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (plus:SF (mult:SF
+			   (neg:SF (match_operand:SF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fmsubs %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (plus:SF (mult:SF
+			   (neg:SF (match_operand:SF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fms|fmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fmsub 4: D = - (C - (A * B))
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+			  (mult:SF
+				(match_operand:SF 1 "gpc_reg_operand" "%f")
+				(match_operand:SF 2 "gpc_reg_operand" "f")))))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fmsubs %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+			  (mult:SF
+				(match_operand:SF 1 "gpc_reg_operand" "%f")
+				(match_operand:SF 2 "gpc_reg_operand" "f")))))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fms|fmsub} %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+
+;; fnmadd 1: D = - (A * B + C)
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
@@ -5293,6 +5358,45 @@
   "{fnma|fnmadd} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fnmadd 2: D = (-A * B) - C
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fnmadds %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+        (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "%f"))
+                           (match_operand:SF 2 "gpc_reg_operand" "f"))
+                  (match_operand:SF 3 "gpc_reg_operand" "f")))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnma|fnmadd} %0,%1,%2,%3"       
+  [(set_attr "type" "dmul")])
+
+;; fnmadd 3: D = - C - (A * B)
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(minus:SF (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))
+		  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fnmadds %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""       
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+        (minus:SF (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))
+                  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+                           (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnma|fnmadd} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 1: D = - (A * B - C)
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
 	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
@@ -5311,6 +5415,63 @@
   "{fnms|fnmsub} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fnmsub 2: D = C - (A * B)
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+		  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fnmsubs %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
+		  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnms|fnmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 3: D = - (-C + (A * B))
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+				   (match_operand:SF 2 "gpc_reg_operand" "f"))
+			 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fnmsubs %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+				   (match_operand:SF 2 "gpc_reg_operand" "f"))
+			 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnms|fnmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 4: D = (- A * B) + C
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(plus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "fnmsubs %0,%1,%2,%3"
+  [(set_attr "type" "fp")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+        (plus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "%f"))
+                           (match_operand:SF 2 "gpc_reg_operand" "f"))   
+                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnms|fnmsub} %0,%1,%2,%3"      
+  [(set_attr "type" "dmul")])
+
 (define_expand "sqrtsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
@@ -5501,6 +5662,7 @@
   "{fd|fdiv} %0,%1,%2"
   [(set_attr "type" "ddiv")])
 
+;; fmadd: D = (A * B) + C
 (define_insn ""
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
@@ -5510,6 +5672,7 @@
   "{fma|fmadd} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fmsub 1: D = (A * B) - C
 (define_insn ""
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
@@ -5519,6 +5682,39 @@
   "{fms|fmsub} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fmsub 2: D = -C + (A * B)
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))
+		 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fms|fmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fmsub 3: D = - ((-A * B) + C)
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (plus:DF (mult:DF
+			   (neg:DF (match_operand:DF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))
+			 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fms|fmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fmsub 4: D = - (C - (A * B))
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
+			  (mult:DF
+				(match_operand:DF 1 "gpc_reg_operand" "%f")
+				(match_operand:DF 2 "gpc_reg_operand" "f")))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fms|fmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmadd 1: D = - (A * B + C)
 (define_insn ""
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
@@ -5528,11 +5724,62 @@
   "{fnma|fnmadd} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])
 
+;; fnmadd 2: D = (-A * B) - C
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))
+		  (match_operand:DF 3 "gpc_reg_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnma|fnmadd} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmadd 3: D = - C - (A * B)
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(minus:DF (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))
+		  (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnma|fnmadd} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 1: D = - (A * B - C)
 (define_insn ""
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 	(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
 				   (match_operand:DF 2 "gpc_reg_operand" "f"))
 			  (match_operand:DF 3 "gpc_reg_operand" "f"))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnms|fnmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 2: D = C - (A * B)
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
+		  (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnms|fnmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 3: D = - (-C + (A * B))
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+				   (match_operand:DF 2 "gpc_reg_operand" "f"))
+			 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
+  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
+  "{fnms|fnmsub} %0,%1,%2,%3"
+  [(set_attr "type" "dmul")])
+
+;; fnmsub 4: D = (- A * B) + C
+(define_insn ""
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(plus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "%f"))
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))
+		 (match_operand:DF 3 "gpc_reg_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
   "{fnms|fnmsub} %0,%1,%2,%3"
   [(set_attr "type" "dmul")])