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IA64 Inline division patch
- From: Steve Ellcey <sje at cup dot hp dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 31 Oct 2002 12:58:45 -0800 (PST)
- Subject: IA64 Inline division patch
- Reply-to: sje at cup dot hp dot com
While doing some experimenting with inline division on IA64 I found that
inlining floating point division was helping performance and inlining
integer division was hurting performance. This patch allows us to do
one without the other by having seperate flags for integer and floating
point inlining.
Steve Ellcey
sje@cup.hp.com
2002-10-31 Steve Ellcey <sje@cup.hp.com>
* config/ia64/ia64.h (MASK_INLINE_DIV_LAT): Remove.
(MASK_INLINE_DIV_THR): Remove.
(TARGET_INLINE_DIV_LAT): Remove.
(TARGET_INLINE_DIV_THR): Remove.
(TARGET_INLINE_DIV): Remove.
(MASK_INLINE_FLOAT_DIV_LAT): New macro.
(MASK_INLINE_FLOAT_DIV_THR): New macro.
(MASK_INLINE_INT_DIV_LAT): New macro.
(MASK_INLINE_INT_DIV_THR): New macro.
(TARGET_INLINE_FLOAT_DIV_LAT): New macro.
(TARGET_INLINE_FLOAT_DIV_THR): New macro.
(TARGET_INLINE_INT_DIV_LAT): New macro.
(TARGET_INLINE_INT_DIV_THR): New macro.
(TARGET_INLINE_FLOAT_DIV): New macro.
(TARGET_INLINE_INT_DIV): New macro.
* config/ia64/ia64.md (divsi3): Change to use new macros.
(modsi3): Ditto.
(udivsi3): Ditto.
(umodsi3): Ditto.
(divsi3_internal): Ditto.
(divdi3): Ditto.
(moddi3): Ditto.
(udivdi3): Ditto.
(umoddi3): Ditto.
(divdi3_internal_lat): Ditto.
(divdi3_internal_thr): Ditto.
(divsf3): Ditto.
(divsf3_internal_lat): Ditto.
(divsf3_internal_thr): Ditto.
(divdf3): Ditto.
(divdf3_internal_lat): Ditto.
(divdf3_internal_thr): Ditto.
(divtf3): Ditto.
(divtf3_internal_lat): Ditto.
(divtf3_internal_thr): Ditto.
* config/ia64/ia64.c (ia64_override_options): Change
to check new macros for conflicts in settings.
*** gcc.orig/gcc/config/ia64/ia64.h Thu Oct 31 10:07:42 2002
--- gcc/gcc/config/ia64/ia64.h Thu Oct 31 10:47:05 2002
*************** extern int target_flags;
*** 85,93 ****
#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
! #define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
! #define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
--- 85,97 ----
#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
! #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
! #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
!
! #define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
!
! #define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
*************** extern int target_flags;
*** 113,124 ****
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
! #define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
! #define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
! #define TARGET_INLINE_DIV \
! (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
--- 117,135 ----
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
! #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
!
! #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
!
! #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
!
! #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
! #define TARGET_INLINE_FLOAT_DIV \
! (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
! #define TARGET_INLINE_INT_DIV \
! (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
*************** extern int ia64_tls_size;
*** 165,174 ****
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
! { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
! N_("Generate inline division, optimize for latency") }, \
! { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
! N_("Generate inline division, optimize for throughput") }, \
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
--- 176,189 ----
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
! { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
! N_("Generate inline floating point division, optimize for latency") },\
! { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
! N_("Generate inline floating point division, optimize for throughput") },\
! { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
! N_("Generate inline integer division, optimize for latency") }, \
! { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
! N_("Generate inline integer division, optimize for throughput") },\
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
*** gcc.orig/gcc/config/ia64/ia64.md Thu Oct 31 10:07:44 2002
--- gcc/gcc/config/ia64/ia64.md Thu Oct 31 10:20:19 2002
***************
*** 1987,1993 ****
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
--- 1987,1993 ----
[(set (match_operand:SI 0 "register_operand" "")
(div:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
***************
*** 2021,2027 ****
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op2_neg, op1_di, div;
--- 2021,2027 ----
[(set (match_operand:SI 0 "register_operand" "")
(mod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, op1_di, div;
***************
*** 2044,2050 ****
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
--- 2044,2050 ----
[(set (match_operand:SI 0 "register_operand" "")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
REAL_VALUE_TYPE twon34_r;
***************
*** 2078,2084 ****
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op2_neg, op1_di, div;
--- 2078,2084 ----
[(set (match_operand:SI 0 "register_operand" "")
(umod:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, op1_di, div;
***************
*** 2105,2111 ****
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2105,2111 ----
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
(use (match_operand:TF 3 "fr_register_operand" "f"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2375,2381 ****
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op1_tf, op2_tf, op0_tf;
--- 2375,2381 ----
[(set (match_operand:DI 0 "register_operand" "")
(div:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf;
***************
*** 2391,2397 ****
op2_tf = gen_reg_rtx (TFmode);
expand_float (op2_tf, operands[2], 0);
! if (TARGET_INLINE_DIV_LAT)
emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
else
emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
--- 2391,2397 ----
op2_tf = gen_reg_rtx (TFmode);
expand_float (op2_tf, operands[2], 0);
! if (TARGET_INLINE_INT_DIV_LAT)
emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
else
emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
***************
*** 2404,2410 ****
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op2_neg, div;
--- 2404,2410 ----
[(set (match_operand:DI 0 "register_operand" "")
(mod:SI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, div;
***************
*** 2421,2427 ****
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op1_tf, op2_tf, op0_tf;
--- 2421,2427 ----
[(set (match_operand:DI 0 "register_operand" "")
(udiv:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op1_tf, op2_tf, op0_tf;
***************
*** 2437,2443 ****
op2_tf = gen_reg_rtx (TFmode);
expand_float (op2_tf, operands[2], 1);
! if (TARGET_INLINE_DIV_LAT)
emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
else
emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
--- 2437,2443 ----
op2_tf = gen_reg_rtx (TFmode);
expand_float (op2_tf, operands[2], 1);
! if (TARGET_INLINE_INT_DIV_LAT)
emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
else
emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
***************
*** 2450,2456 ****
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx op2_neg, div;
--- 2450,2456 ----
[(set (match_operand:DI 0 "register_operand" "")
(umod:DI (match_operand:DI 1 "general_operand" "")
(match_operand:DI 2 "general_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
{
rtx op2_neg, div;
***************
*** 2471,2477 ****
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2471,2477 ----
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2530,2536 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 2530,2536 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 2681,2690 ****
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx insn;
! if (TARGET_INLINE_DIV_LAT)
insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
--- 2681,2690 ----
[(set (match_operand:SF 0 "fr_register_operand" "")
(div:SF (match_operand:SF 1 "fr_register_operand" "")
(match_operand:SF 2 "fr_register_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
! if (TARGET_INLINE_FLOAT_DIV_LAT)
insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
***************
*** 2699,2705 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 2699,2705 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 2756,2762 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 2756,2762 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 2990,2999 ****
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx insn;
! if (TARGET_INLINE_DIV_LAT)
insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
--- 2990,2999 ----
[(set (match_operand:DF 0 "fr_register_operand" "")
(div:DF (match_operand:DF 1 "fr_register_operand" "")
(match_operand:DF 2 "fr_register_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
! if (TARGET_INLINE_FLOAT_DIV_LAT)
insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
***************
*** 3009,3015 ****
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
--- 3009,3015 ----
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
***************
*** 3089,3095 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
--- 3089,3095 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
***************
*** 3467,3476 ****
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
{
rtx insn;
! if (TARGET_INLINE_DIV_LAT)
insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
--- 3467,3476 ----
[(set (match_operand:TF 0 "fr_register_operand" "")
(div:TF (match_operand:TF 1 "fr_register_operand" "")
(match_operand:TF 2 "fr_register_operand" "")))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
! if (TARGET_INLINE_FLOAT_DIV_LAT)
insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
***************
*** 3487,3493 ****
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 3487,3493 ----
(clobber (match_scratch:TF 5 "=&f"))
(clobber (match_scratch:TF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
***************
*** 3565,3571 ****
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
--- 3565,3571 ----
(clobber (match_scratch:TF 3 "=&f"))
(clobber (match_scratch:TF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
! "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
*** gcc.orig/gcc/config/ia64/ia64.c Thu Oct 31 10:52:04 2002
--- gcc/gcc/config/ia64/ia64.c Thu Oct 31 10:53:24 2002
*************** ia64_override_options ()
*** 4161,4170 ****
if (TARGET_AUTO_PIC)
target_flags |= MASK_CONST_GP;
! if (TARGET_INLINE_DIV_LAT && TARGET_INLINE_DIV_THR)
{
! warning ("cannot optimize division for both latency and throughput");
! target_flags &= ~MASK_INLINE_DIV_THR;
}
if (ia64_fixed_range_string)
--- 4161,4176 ----
if (TARGET_AUTO_PIC)
target_flags |= MASK_CONST_GP;
! if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
{
! warning ("cannot optimize floating point division for both latency and throughput");
! target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
! }
!
! if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
! {
! warning ("cannot optimize integer division for both latency and throughput");
! target_flags &= ~MASK_INLINE_INT_DIV_THR;
}
if (ia64_fixed_range_string)