This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

A few more PowerPC TFmode fixes


	* config/rs6000/rs6000.md (extenddftf2): Change to define_insn
	which copies first FPR and clears second.
	(extendsftf2): Same.
	(floatditf2): Fix typo.
	(floatsitf2): Same.
	(fix_trunctfdi2): Same.
	(fix_trunctfsi2): Same.

Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.215
diff -c -p -r1.215 rs6000.md
*** rs6000.md	9 Oct 2002 04:28:12 -0000	1.215
--- rs6000.md	9 Oct 2002 20:44:35 -0000
***************
*** 8516,8523 ****
    operands[2] = gen_lowpart (DImode, operands[0]);
    /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN.  */
  #if HOST_BITS_PER_WIDE_INT >= 64
!   val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
!         ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
  
    operands[3] = gen_int_mode (val, DImode);
  #else
--- 8516,8523 ----
    operands[2] = gen_lowpart (DImode, operands[0]);
    /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN.  */
  #if HOST_BITS_PER_WIDE_INT >= 64
!   val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
!          | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
  
    operands[3] = gen_int_mode (val, DImode);
  #else
***************
*** 8797,8808 ****
    operands[2] = gen_lowpart (DImode, operands[0]);
    operands[3] = gen_highpart (DImode, operands[0]);
  #if HOST_BITS_PER_WIDE_INT >= 64
!   val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32 |
!         ((HOST_WIDE_INT)(unsigned long)l[1]));
    operands[4] = gen_int_mode (val, DImode);
  
!   val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32 |
!         ((HOST_WIDE_INT)(unsigned long)l[3]));
    operands[5] = gen_int_mode (val, DImode);
  #else
    operands[4] = immed_double_const (l[1], l[0], DImode);
--- 8797,8808 ----
    operands[2] = gen_lowpart (DImode, operands[0]);
    operands[3] = gen_highpart (DImode, operands[0]);
  #if HOST_BITS_PER_WIDE_INT >= 64
!   val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
!          | ((HOST_WIDE_INT)(unsigned long)l[1]));
    operands[4] = gen_int_mode (val, DImode);
  
!   val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
!          | ((HOST_WIDE_INT)(unsigned long)l[3]));
    operands[5] = gen_int_mode (val, DImode);
  #else
    operands[4] = immed_double_const (l[1], l[0], DImode);
***************
*** 8810,8842 ****
  #endif
  }")
  
! (define_insn_and_split "extenddftf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
  	(float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
    "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
     && TARGET_LONG_DOUBLE_128"
!   "#"
!   ""
!   [(set (match_dup 2) (match_dup 3))]
!   "
  {
!   operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1));
!   operands[3] = CONST0_RTX (DFmode);
! }")
  
! (define_insn_and_split "extendsftf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
  	(float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
    "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
     && TARGET_LONG_DOUBLE_128"
!   "#"
!   ""
!   [(set (match_dup 2) (match_dup 3))]
!   "
  {
!   operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1));
!   operands[3] = CONST0_RTX (SFmode);
! }")
  
  (define_insn "trunctfdf2"
    [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
--- 8810,8842 ----
  #endif
  }")
  
! (define_insn "extenddftf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
  	(float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
    "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
     && TARGET_LONG_DOUBLE_128"
!   "*
  {
!   if (REGNO (operands[0]) == REGNO (operands[1]))
!     return \"fsub %L0,%L0,%L0\";
!   else
!     return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
! }"
!   [(set_attr "type" "fp")])
  
! (define_insn "extendsftf2"
    [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
  	(float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
    "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
     && TARGET_LONG_DOUBLE_128"
!   "*
  {
!   if (REGNO (operands[0]) == REGNO (operands[1]))
!     return \"fsub %L0,%L0,%L0\";
!   else
!     return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
! }"
!   [(set_attr "type" "fp")])
  
  (define_insn "trunctfdf2"
    [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
***************
*** 8870,8877 ****
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
!    (set (match_operand:TF 0 "gpc_reg_operand" "")
  	(float_extend:TF (match_dup 2)))]
    "")
  
--- 8870,8877 ----
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float:DF (match_dup 1)))
!    (set (match_dup 0)
  	(float_extend:TF (match_dup 2)))]
    "")
  
***************
*** 8884,8917 ****
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
!    (set (match_operand:TF 0 "gpc_reg_operand" "")
  	(float_extend:TF (match_dup 2)))]
    "")
  
  (define_insn_and_split "fix_trunctfdi2"
    [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
!         (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
    "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
     && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
!    (set (match_operand:DI 0 "gpc_reg_operand" "")
! 	(fix:SI (match_dup 2)))]
    "")
  
  (define_insn_and_split "fix_trunctfsi2"
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
!         (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
    "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
     && TARGET_LONG_DOUBLE_128"
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
!    (set (match_operand:SI 0 "gpc_reg_operand" "")
  	(fix:SI (match_dup 2)))]
    "")
  
--- 8884,8919 ----
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float:DF (match_dup 1)))
!    (set (match_dup 0)
  	(float_extend:TF (match_dup 2)))]
    "")
  
  (define_insn_and_split "fix_trunctfdi2"
    [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
!         (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
!    (clobber (match_scratch:DF 2 "=f"))]
    "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
     && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float_truncate:DF (match_dup 1)))
!    (set (match_dup 0)
! 	(fix:DI (match_dup 2)))]
    "")
  
  (define_insn_and_split "fix_trunctfsi2"
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
!         (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
!    (clobber (match_scratch:DF 2 "=f"))]
    "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
     && TARGET_LONG_DOUBLE_128"
    "#"
    "&& reload_completed"
    [(set (match_dup 2)
! 	(float_truncate:DF (match_dup 1)))
!    (set (match_dup 0)
  	(fix:SI (match_dup 2)))]
    "")
  


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]