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Re: [itanium-sched-branch] Preparation for Itanium2 DFA description [patch]
The following patch is a preparation for adding DFA description of
Itanium2. Usage of -mcpu=itanium2 will not work until DFA Itanium2
description is added (it will happen probably in a week).
Vlad
2002-10-08 Vladimir Makarov <vmakarov@redhat.com>
* config/ia64/ia64.h (processor_type): New enumeration.
(ia64_cpu, ia64_cpu_string): New external declarations.
(TARGET_OPTIONS): Add option `cpu='.
* config/ia64/ia64.c (ia64_cpu, ia64_cpu_string): New global
variables.
(ia64_override_options): Set up `ia64_cpu'.
(ia64_sched_reorder2): Set up `clocks' only for Itanium.
(ia64_dfa_new_cycle): Set up `add_cycles' only for Itanium.
(bundling): Add nops for MM-insns only for Itanium.
(ia64_reorg): Allocate and free `clocks' and `add_cycles' only
for
Itanium.
* config/ia64/ia64.md (cpu): New attribute.
(DFA description): Enable it only for Itanium.
Index: config/ia64/ia64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.h,v
retrieving revision 1.126.4.3
diff -d -c -p -r1.126.4.3 ia64.h
*** config/ia64/ia64.h 8 Oct 2002 20:40:09 -0000 1.126.4.3
--- config/ia64/ia64.h 8 Oct 2002 21:42:05 -0000
*************** extern int ia64_tls_size;
*** 205,216 ****
--- 205,234 ----
extern const char *ia64_fixed_range_string;
extern const char *ia64_tls_size_string;
+
+ /* Which processor to schedule for. The cpu attribute defines a list
+ that mirrors this list, so changes to i64.md must be made at the
+ same time. */
+
+ enum processor_type
+ {
+ PROCESSOR_ITANIUM, /* Original Itanium. */
+ PROCESSOR_ITANIUM2,
+ PROCESSOR_max
+ };
+
+ extern enum processor_type ia64_cpu;
+
+ extern const char *ia64_cpu_string;
+
#define TARGET_OPTIONS \
{ \
{ "fixed-range=", &ia64_fixed_range_string, \
N_("Specify range of registers to make fixed")}, \
{ "tls-size=", &ia64_tls_size_string, \
N_("Specify bit size of immediate TLS offsets")}, \
+ { "cpu=", &ia64_cpu_string, \
+ N_("Schedule code for given CPU")}, \
}
/* Sometimes certain combinations of command options do not make sense on a
Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.184.4.6
diff -d -c -p -r1.184.4.6 ia64.c
*** config/ia64/ia64.c 8 Oct 2002 20:40:10 -0000 1.184.4.6
--- config/ia64/ia64.c 8 Oct 2002 21:42:06 -0000
*************** int ia64_tls_size = 22;
*** 102,107 ****
--- 102,113 ----
/* String used with the -mtls-size= option. */
const char *ia64_tls_size_string;
+ /* Which cpu are we scheduling for. */
+ enum processor_type ia64_cpu;
+
+ /* String used with the -mcpu= option. */
+ const char *ia64_cpu_string;
+
/* Determines whether we run our final scheduling pass or not. We always
avoid the normal second scheduling pass. */
static int ia64_flag_schedule_insns2;
*************** ia64_init_machine_status ()
*** 4208,4213 ****
--- 4214,4233 ----
void
ia64_override_options ()
{
+ static struct pta
+ {
+ const char *const name; /* processor name or nickname. */
+ const enum processor_type processor;
+ }
+ const processor_alias_table[] =
+ {
+ {"itanium", PROCESSOR_ITANIUM},
+ {"itanium2", PROCESSOR_ITANIUM2},
+ };
+
+ int const pta_size = ARRAY_SIZE (processor_alias_table);
+ int i;
+
if (TARGET_AUTO_PIC)
target_flags |= MASK_CONST_GP;
*************** ia64_override_options ()
*** 4230,4235 ****
--- 4250,4268 ----
ia64_tls_size = tmp;
}
+ if (!ia64_cpu_string)
+ ia64_cpu_string = "itanium";
+
+ for (i = 0; i < pta_size; i++)
+ if (! strcmp (ia64_cpu_string, processor_alias_table[i].name))
+ {
+ ia64_cpu = processor_alias_table[i].processor;
+ break;
+ }
+
+ if (i == pta_size)
+ error ("bad value (%s) for -mcpu= switch", ia64_cpu_string);
+
ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
flag_schedule_insns_after_reload = 0;
*************** static int stop_before_p = 0;
*** 5430,5441 ****
static int clocks_length;
/* The following array element values are cycles on which the
! corresponding insn will be issued. */
static int *clocks;
/* The following array element values are numbers of cycles should be
! added to improve insn scheduling for MM_insns for Itanium1. */
static int *add_cycles;
--- 5463,5475 ----
static int clocks_length;
/* The following array element values are cycles on which the
! corresponding insn will be issued. The array is used only for
! Itanium1. */
static int *clocks;
/* The following array element values are numbers of cycles should be
! added to improve insn scheduling for MM_insns for Itanium1. */
static int *add_cycles;
*************** ia64_sched_reorder2 (dump, sched_verbose
*** 5700,5706 ****
int *pn_ready;
int clock_var;
{
! if (reload_completed && last_scheduled_insn)
clocks [INSN_UID (last_scheduled_insn)] = clock_var;
return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
clock_var, 1);
--- 5734,5740 ----
int *pn_ready;
int clock_var;
{
! if (ia64_cpu == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
clocks [INSN_UID (last_scheduled_insn)] = clock_var;
return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
clock_var, 1);
*************** ia64_dfa_new_cycle (dump, verbose, insn,
*** 5795,5801 ****
}
else if (reload_completed)
setup_clocks_p = TRUE;
! if (setup_clocks_p)
{
enum attr_itanium_class c = ia64_safe_itanium_class (insn);
--- 5829,5835 ----
}
else if (reload_completed)
setup_clocks_p = TRUE;
! if (setup_clocks_p && ia64_cpu == PROCESSOR_ITANIUM)
{
enum attr_itanium_class c = ia64_safe_itanium_class (insn);
*************** bundling (dump, verbose, prev_head_insn,
*** 6530,6598 ****
}
}
}
! /* Insert additional cycles for MM-insns: */
! for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
! insn != NULL_RTX;
! insn = next_insn)
! {
! if (!INSN_P (insn)
! || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
! || GET_CODE (PATTERN (insn)) == USE
! || GET_CODE (PATTERN (insn)) == CLOBBER)
! abort ();
! next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
! if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
! {
! rtx last;
! int i, j, n;
! int pred_stop_p;
!
! last = prev_active_insn (insn);
! pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
! if (pred_stop_p)
! last = prev_active_insn (last);
! n = 0;
! for (;; last = prev_active_insn (last))
! if (recog_memoized (last) == CODE_FOR_bundle_selector)
! {
! template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
! break;
! }
! else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
! n++;
! if ((pred_stop_p && n == 0) || n > 2)
! abort ();
! for (j = 3 - n; j > 0; j --)
! ia64_emit_insn_before (gen_nop (), insn);
! add_cycles [INSN_UID (insn)]--;
! if (!pred_stop_p || add_cycles [INSN_UID (insn)])
! ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
! if (pred_stop_p)
! add_cycles [INSN_UID (insn)]--;
! for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
! {
! /* Insert .MII bundle. */
! ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)), insn);
! ia64_emit_insn_before (gen_nop (), insn);
! ia64_emit_insn_before (gen_nop (), insn);
! if (i > 1)
{
! ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
! insn);
! i--;
}
ia64_emit_insn_before (gen_nop (), insn);
ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
insn);
! }
! ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
! insn);
! for (j = n; j > 0; j --)
! ia64_emit_insn_before (gen_nop (), insn);
! if (pred_stop_p)
! ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
! }
! }
free (index_to_bundle_states);
finish_bundle_state_table ();
bundling_p = 0;
--- 6564,6636 ----
}
}
}
! if (ia64_cpu == PROCESSOR_ITANIUM)
! /* Insert additional cycles for MM-insns: */
! for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
! insn != NULL_RTX;
! insn = next_insn)
! {
! if (!INSN_P (insn)
! || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
! || GET_CODE (PATTERN (insn)) == USE
! || GET_CODE (PATTERN (insn)) == CLOBBER)
! abort ();
! next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
! if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
! {
! rtx last;
! int i, j, n;
! int pred_stop_p;
!
! last = prev_active_insn (insn);
! pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
! if (pred_stop_p)
! last = prev_active_insn (last);
! n = 0;
! for (;; last = prev_active_insn (last))
! if (recog_memoized (last) == CODE_FOR_bundle_selector)
{
! template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
! break;
}
+ else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
+ n++;
+ if ((pred_stop_p && n == 0) || n > 2)
+ abort ();
+ for (j = 3 - n; j > 0; j --)
ia64_emit_insn_before (gen_nop (), insn);
+ add_cycles [INSN_UID (insn)]--;
+ if (!pred_stop_p || add_cycles [INSN_UID (insn)])
ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
insn);
! if (pred_stop_p)
! add_cycles [INSN_UID (insn)]--;
! for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
! {
! /* Insert .MII bundle. */
! ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
! insn);
! ia64_emit_insn_before (gen_nop (), insn);
! ia64_emit_insn_before (gen_nop (), insn);
! if (i > 1)
! {
! ia64_emit_insn_before
! (gen_insn_group_barrier (GEN_INT (3)), insn);
! i--;
! }
! ia64_emit_insn_before (gen_nop (), insn);
! ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
! insn);
! }
! ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
! insn);
! for (j = n; j > 0; j --)
! ia64_emit_insn_before (gen_nop (), insn);
! if (pred_stop_p)
! ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
! insn);
! }
! }
free (index_to_bundle_states);
finish_bundle_state_table ();
bundling_p = 0;
*************** ia64_reorg (insns)
*** 6916,6925 ****
clocks_length = get_max_uid () + 1;
stops_p = (char *) xmalloc (clocks_length);
memset (stops_p, 0, clocks_length);
! clocks = (int *) xmalloc (clocks_length * sizeof (int));
! memset (clocks, 0, clocks_length * sizeof (int));
! add_cycles = (int *) xmalloc (clocks_length * sizeof (int));
! memset (add_cycles, 0, clocks_length * sizeof (int));
pos_1 = get_cpu_unit_code ("1_1");
pos_2 = get_cpu_unit_code ("1_2");
pos_3 = get_cpu_unit_code ("1_3");
--- 6954,6966 ----
clocks_length = get_max_uid () + 1;
stops_p = (char *) xmalloc (clocks_length);
memset (stops_p, 0, clocks_length);
! if (ia64_cpu == PROCESSOR_ITANIUM)
! {
! clocks = (int *) xmalloc (clocks_length * sizeof (int));
! memset (clocks, 0, clocks_length * sizeof (int));
! add_cycles = (int *) xmalloc (clocks_length * sizeof (int));
! memset (add_cycles, 0, clocks_length * sizeof (int));
! }
pos_1 = get_cpu_unit_code ("1_1");
pos_2 = get_cpu_unit_code ("1_2");
pos_3 = get_cpu_unit_code ("1_3");
*************** ia64_reorg (insns)
*** 6949,6956 ****
schedule_ebbs (rtl_dump_file);
finish_bundle_states ();
! free (add_cycles);
! free (clocks);
free (stops_p);
emit_insn_group_barriers (rtl_dump_file, insns);
--- 6990,7000 ----
schedule_ebbs (rtl_dump_file);
finish_bundle_states ();
! if (ia64_cpu == PROCESSOR_ITANIUM)
! {
! free (add_cycles);
! free (clocks);
! }
free (stops_p);
emit_insn_group_barriers (rtl_dump_file, insns);
Index: config/ia64/ia64.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.md,v
retrieving revision 1.90.10.4
diff -d -c -p -r1.90.10.4 ia64.md
*** config/ia64/ia64.md 8 Oct 2002 20:40:10 -0000 1.90.10.4
--- config/ia64/ia64.md 8 Oct 2002 21:42:06 -0000
***************
*** 91,96 ****
--- 91,100 ----
;; ::
;; ::::::::::::::::::::
+ ;; Processor type. This attribute must exactly match the processor_type
+ ;; enumeration in ia64.h.
+ (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_cpu")))
+
;; Instruction type. This primarily determines how instructions can be
;; packed in bundles, and secondarily affects scheduling to function units.
***************
*** 713,886 ****
(define_reservation "1_A" "1_M|1_I")
(define_insn_reservation "1_stop_bit" 0
! (and (eq_attr "itanium_class" "stop_bit")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop")
(define_insn_reservation "1_br" 0
! (and (eq_attr "itanium_class" "br")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
(define_insn_reservation "1_scall" 0
! (and (eq_attr "itanium_class" "scall")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
(define_insn_reservation "1_fcmp" 2
! (and (eq_attr "itanium_class" "fcmp")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_F+1_not_uf1")
(define_insn_reservation "1_fcvtfx" 7
! (and (eq_attr "itanium_class" "fcvtfx")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fld" 9
! (and (eq_attr "itanium_class" "fld")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fmac" 5
! (and (eq_attr "itanium_class" "fmac")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fmisc" 5
! (and (eq_attr "itanium_class" "fmisc")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_F+1_not_uf1")
;; There is only one insn `mov = ar.bsp' for frar_i:
(define_insn_reservation "1_frar_i" 13
! (and (eq_attr "itanium_class" "frar_i")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m:
(define_insn_reservation "1_frar_m" 6
! (and (eq_attr "itanium_class" "frar_m")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_frbr" 2
! (and (eq_attr "itanium_class" "frbr")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_frfr" 2
! (and (eq_attr "itanium_class" "frfr")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_frpr" 2
! (and (eq_attr "itanium_class" "frpr")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_ialu" 1
! (and (eq_attr "itanium_class" "ialu")
(eq (symbol_ref
"bundling_p || ia64_produce_address_p (insn)")
(const_int 0)))
"1_A")
(define_insn_reservation "1_ialu_addr" 1
! (and (eq_attr "itanium_class" "ialu")
(eq (symbol_ref
"!bundling_p && ia64_produce_address_p (insn)")
(const_int 1)))
"1_M")
(define_insn_reservation "1_icmp" 1
! (and (eq_attr "itanium_class" "icmp")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_ilog" 1
! (and (eq_attr "itanium_class" "ilog")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_ishf" 1
! (and (eq_attr "itanium_class" "ishf")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_ld" 2
! (and (eq_attr "itanium_class" "ld")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_long_i" 1
! (and (eq_attr "itanium_class" "long_i")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_L")
(define_insn_reservation "1_mmmul" 2
! (and (eq_attr "itanium_class" "mmmul")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_mmshf" 2
! (and (eq_attr "itanium_class" "mmshf")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
(define_insn_reservation "1_mmshfi" 1
! (and (eq_attr "itanium_class" "mmshfi")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
;; Now we have only one insn (flushrs) of such class. We assume that flushrs
;; is the 1st syllable of the bundle after stop bit.
(define_insn_reservation "1_rse_m" 0
! (and (eq_attr "itanium_class" "rse_m")
(eq (symbol_ref "bundling_p") (const_int 0)))
"(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\
|1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0")
(define_insn_reservation "1_sem" 0
! (and (eq_attr "itanium_class" "sem")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_stf" 1
! (and (eq_attr "itanium_class" "stf")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_st" 1
! (and (eq_attr "itanium_class" "st")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_syst_m0" 0
! (and (eq_attr "itanium_class" "syst_m0")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_syst_m" 0
! (and (eq_attr "itanium_class" "syst_m")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_tbit" 1
! (and (eq_attr "itanium_class" "tbit")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
;; There is only ony insn `mov ar.pfs =' for toar_i:
(define_insn_reservation "1_toar_i" 0
! (and (eq_attr "itanium_class" "toar_i")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
(define_insn_reservation "1_toar_m" 5
! (and (eq_attr "itanium_class" "toar_m")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_tobr" 1
! (and (eq_attr "itanium_class" "tobr")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_tofr" 9
! (and (eq_attr "itanium_class" "tofr")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_topr" 1
! (and (eq_attr "itanium_class" "topr")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_xmpy" 7
! (and (eq_attr "itanium_class" "xmpy")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_xtd" 1
! (and (eq_attr "itanium_class" "xtd")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
(define_insn_reservation "1_chk_s" 0
! (and (eq_attr "itanium_class" "chk_s")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_lfetch" 0
! (and (eq_attr "itanium_class" "lfetch")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_nop_m" 0
! (and (eq_attr "itanium_class" "nop_m")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M0")
(define_insn_reservation "1_nop_b" 0
! (and (eq_attr "itanium_class" "nop_b")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_NB")
(define_insn_reservation "1_nop_i" 0
! (and (eq_attr "itanium_class" "nop_i")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I0")
(define_insn_reservation "1_nop_f" 0
! (and (eq_attr "itanium_class" "nop_f")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F0")
(define_insn_reservation "1_nop_x" 0
! (and (eq_attr "itanium_class" "nop_x")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_L0")
;; We assume that there is no insn issued on the same cycle as unknown insn.
--- 717,934 ----
(define_reservation "1_A" "1_M|1_I")
(define_insn_reservation "1_stop_bit" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "stop_bit"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop")
(define_insn_reservation "1_br" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "br"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
(define_insn_reservation "1_scall" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "scall"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_B")
(define_insn_reservation "1_fcmp" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fcmp"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_F+1_not_uf1")
(define_insn_reservation "1_fcvtfx" 7
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fcvtfx"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fld" 9
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fld"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_fmac" 5
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fmac"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_fmisc" 5
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fmisc"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_F+1_not_uf1")
;; There is only one insn `mov = ar.bsp' for frar_i:
(define_insn_reservation "1_frar_i" 13
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frar_i"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m:
(define_insn_reservation "1_frar_m" 6
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frar_m"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_frbr" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frbr"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_frfr" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frfr"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_frpr" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frpr"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_ialu" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ialu"))
(eq (symbol_ref
"bundling_p || ia64_produce_address_p (insn)")
(const_int 0)))
"1_A")
(define_insn_reservation "1_ialu_addr" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ialu"))
(eq (symbol_ref
"!bundling_p && ia64_produce_address_p (insn)")
(const_int 1)))
"1_M")
(define_insn_reservation "1_icmp" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "icmp"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_ilog" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ilog"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_ishf" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ishf"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_ld" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ld"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_long_i" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "long_i"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_L")
(define_insn_reservation "1_mmmul" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "mmmul"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_mmshf" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "mmshf"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
(define_insn_reservation "1_mmshfi" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "mmshfi"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
;; Now we have only one insn (flushrs) of such class. We assume that flushrs
;; is the 1st syllable of the bundle after stop bit.
(define_insn_reservation "1_rse_m" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "rse_m"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\
|1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0")
(define_insn_reservation "1_sem" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "sem"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_stf" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "stf"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_st" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "st"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_syst_m0" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "syst_m0"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_syst_m" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "syst_m"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_tbit" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "tbit"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
;; There is only ony insn `mov ar.pfs =' for toar_i:
(define_insn_reservation "1_toar_i" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "toar_i"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
(define_insn_reservation "1_toar_m" 5
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "toar_m"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M+1_not_um1")
(define_insn_reservation "1_tobr" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "tobr"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_tofr" 9
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "tofr"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_topr" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "topr"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_I+1_not_ui1")
(define_insn_reservation "1_xmpy" 7
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "xmpy"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
(define_insn_reservation "1_xtd" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "xtd"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
(define_insn_reservation "1_chk_s" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "chk_s"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
(define_insn_reservation "1_lfetch" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "lfetch"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
(define_insn_reservation "1_nop_m" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_m"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_M0")
(define_insn_reservation "1_nop_b" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_b"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_NB")
(define_insn_reservation "1_nop_i" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_i"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_I0")
(define_insn_reservation "1_nop_f" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_f"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_F0")
(define_insn_reservation "1_nop_x" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_x"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_L0")
;; We assume that there is no insn issued on the same cycle as unknown insn.
***************
*** 890,905 ****
1_0m.lx")
(define_insn_reservation "1_unknown" 1
! (and (eq_attr "itanium_class" "unknown")
(eq (symbol_ref "bundling_p") (const_int 0))) "1_empty")
(define_insn_reservation "1_nop" 1
! (and (eq_attr "itanium_class" "nop")
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M0|1_NB|1_I0|1_F0")
(define_insn_reservation "1_ignore" 0
! (and (eq_attr "itanium_class" "ignore")
(eq (symbol_ref "bundling_p") (const_int 0))) "nothing")
--- 938,956 ----
1_0m.lx")
(define_insn_reservation "1_unknown" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "unknown"))
(eq (symbol_ref "bundling_p") (const_int 0))) "1_empty")
(define_insn_reservation "1_nop" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"1_M0|1_NB|1_I0|1_F0")
(define_insn_reservation "1_ignore" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ignore"))
(eq (symbol_ref "bundling_p") (const_int 0))) "nothing")
***************
*** 1042,1048 ****
(exclusion_set "1_bb_cont_only" "1_0bbb.")
(define_insn_reservation "1_pre_cycle" 0
! (and (eq_attr "itanium_class" "pre_cycle")
(eq (symbol_ref "bundling_p") (const_int 0)))
"(1_0m_bs, 1_m_cont) \
| (1_0mi_bs, (1_mi_cont|nothing)) \
--- 1093,1100 ----
(exclusion_set "1_bb_cont_only" "1_0bbb.")
(define_insn_reservation "1_pre_cycle" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "pre_cycle"))
(eq (symbol_ref "bundling_p") (const_int 0)))
"(1_0m_bs, 1_m_cont) \
| (1_0mi_bs, (1_mi_cont|nothing)) \
***************
*** 1539,1715 ****
(define_reservation "1b_A" "1b_M|1b_I")
(define_insn_reservation "1b_stop_bit" 0
! (and (eq_attr "itanium_class" "stop_bit")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop")
(define_insn_reservation "1b_br" 0
! (and (eq_attr "itanium_class" "br")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")
(define_insn_reservation "1b_scall" 0
! (and (eq_attr "itanium_class" "scall")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")
(define_insn_reservation "1b_fcmp" 2
! (and (eq_attr "itanium_class" "fcmp")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_F+1b_not_uf1")
(define_insn_reservation "1b_fcvtfx" 7
! (and (eq_attr "itanium_class" "fcvtfx")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_fld" 9
! (and (eq_attr "itanium_class" "fld")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_fmac" 5
! (and (eq_attr "itanium_class" "fmac")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_fmisc" 5
! (and (eq_attr "itanium_class" "fmisc")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_F+1b_not_uf1")
(define_insn_reservation "1b_frar_i" 13
! (and (eq_attr "itanium_class" "frar_i")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_frar_m" 6
! (and (eq_attr "itanium_class" "frar_m")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_frbr" 2
! (and (eq_attr "itanium_class" "frbr")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_frfr" 2
! (and (eq_attr "itanium_class" "frfr")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_frpr" 2
! (and (eq_attr "itanium_class" "frpr")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_ialu" 1
! (and (eq_attr "itanium_class" "ialu")
(ne (symbol_ref
"bundling_p && !ia64_produce_address_p (insn)")
(const_int 0)))
"1b_A")
(define_insn_reservation "1b_ialu_addr" 1
! (and (eq_attr "itanium_class" "ialu")
(eq (symbol_ref
"bundling_p && ia64_produce_address_p (insn)")
(const_int 1)))
"1b_M")
(define_insn_reservation "1b_icmp" 1
! (and (eq_attr "itanium_class" "icmp")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_ilog" 1
! (and (eq_attr "itanium_class" "ilog")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_ishf" 1
! (and (eq_attr "itanium_class" "ishf")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_ld" 2
! (and (eq_attr "itanium_class" "ld")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_long_i" 1
! (and (eq_attr "itanium_class" "long_i")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
(define_insn_reservation "1b_mmmul" 2
! (and (eq_attr "itanium_class" "mmmul")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_mmshf" 2
! (and (eq_attr "itanium_class" "mmshf")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_mmshfi" 2
! (and (eq_attr "itanium_class" "mmshfi")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_rse_m" 0
! (and (eq_attr "itanium_class" "rse_m")
(ne (symbol_ref "bundling_p") (const_int 0)))
"(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\
|1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0")
(define_insn_reservation "1b_sem" 0
! (and (eq_attr "itanium_class" "sem")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_stf" 1
! (and (eq_attr "itanium_class" "stf")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_st" 1
! (and (eq_attr "itanium_class" "st")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_syst_m0" 0
! (and (eq_attr "itanium_class" "syst_m0")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_syst_m" 0
! (and (eq_attr "itanium_class" "syst_m")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_tbit" 1
! (and (eq_attr "itanium_class" "tbit")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_toar_i" 0
! (and (eq_attr "itanium_class" "toar_i")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_toar_m" 5
! (and (eq_attr "itanium_class" "toar_m")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_tobr" 1
! (and (eq_attr "itanium_class" "tobr")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_tofr" 9
! (and (eq_attr "itanium_class" "tofr")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_topr" 1
! (and (eq_attr "itanium_class" "topr")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_xmpy" 7
! (and (eq_attr "itanium_class" "xmpy")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_xtd" 1
! (and (eq_attr "itanium_class" "xtd")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_chk_s" 0
! (and (eq_attr "itanium_class" "chk_s")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_lfetch" 0
! (and (eq_attr "itanium_class" "lfetch")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_nop_m" 0
! (and (eq_attr "itanium_class" "nop_m")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_nop_b" 0
! (and (eq_attr "itanium_class" "nop_b")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_NB")
(define_insn_reservation "1b_nop_i" 0
! (and (eq_attr "itanium_class" "nop_i")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_nop_f" 0
! (and (eq_attr "itanium_class" "nop_f")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_nop_x" 0
! (and (eq_attr "itanium_class" "nop_x")
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
(define_insn_reservation "1b_unknown" 1
! (and (eq_attr "itanium_class" "unknown")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_empty")
(define_insn_reservation "1b_nop" 1
! (and (eq_attr "itanium_class" "nop")
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M|1b_NB|1b_I|1b_F")
(define_insn_reservation "1b_ignore" 0
! (and (eq_attr "itanium_class" "ignore")
(ne (symbol_ref "bundling_p") (const_int 0)))
"nothing")
(define_insn_reservation "1b_pre_cycle" 0
! (and (eq_attr "itanium_class" "pre_cycle")
(ne (symbol_ref "bundling_p") (const_int 0)))
"(1b_0m_bs, 1b_m_cont) \
| (1b_0mi_bs, 1b_mi_cont) \
--- 1591,1815 ----
(define_reservation "1b_A" "1b_M|1b_I")
(define_insn_reservation "1b_stop_bit" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "stop_bit"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop")
(define_insn_reservation "1b_br" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "br"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")
(define_insn_reservation "1b_scall" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "scall"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_B")
(define_insn_reservation "1b_fcmp" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fcmp"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_F+1b_not_uf1")
(define_insn_reservation "1b_fcvtfx" 7
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fcvtfx"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_fld" 9
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fld"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_fmac" 5
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fmac"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_fmisc" 5
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "fmisc"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_F+1b_not_uf1")
(define_insn_reservation "1b_frar_i" 13
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frar_i"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_frar_m" 6
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frar_m"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_frbr" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frbr"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_frfr" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frfr"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_frpr" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "frpr"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_ialu" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ialu"))
(ne (symbol_ref
"bundling_p && !ia64_produce_address_p (insn)")
(const_int 0)))
"1b_A")
(define_insn_reservation "1b_ialu_addr" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ialu"))
(eq (symbol_ref
"bundling_p && ia64_produce_address_p (insn)")
(const_int 1)))
"1b_M")
(define_insn_reservation "1b_icmp" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "icmp"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_ilog" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ilog"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_ishf" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ishf"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_ld" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ld"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_long_i" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "long_i"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
(define_insn_reservation "1b_mmmul" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "mmmul"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_mmshf" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "mmshf"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_mmshfi" 2
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "mmshfi"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_rse_m" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "rse_m"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\
|1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0")
(define_insn_reservation "1b_sem" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "sem"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_stf" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "stf"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_st" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "st"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_syst_m0" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "syst_m0"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_syst_m" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "syst_m"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_tbit" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "tbit"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_toar_i" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "toar_i"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_toar_m" 5
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "toar_m"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M+1b_not_um1")
(define_insn_reservation "1b_tobr" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "tobr"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_tofr" 9
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "tofr"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_topr" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "topr"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_I+1b_not_ui1")
(define_insn_reservation "1b_xmpy" 7
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "xmpy"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_xtd" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "xtd"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_chk_s" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "chk_s"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
(define_insn_reservation "1b_lfetch" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "lfetch"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_nop_m" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_m"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
(define_insn_reservation "1b_nop_b" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_b"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_NB")
(define_insn_reservation "1b_nop_i" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_i"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
(define_insn_reservation "1b_nop_f" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_f"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
(define_insn_reservation "1b_nop_x" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop_x"))
(ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
(define_insn_reservation "1b_unknown" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "unknown"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_empty")
(define_insn_reservation "1b_nop" 1
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "nop"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"1b_M|1b_NB|1b_I|1b_F")
(define_insn_reservation "1b_ignore" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "ignore"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"nothing")
(define_insn_reservation "1b_pre_cycle" 0
! (and (and (eq_attr "cpu" "itanium")
! (eq_attr "itanium_class" "pre_cycle"))
(ne (symbol_ref "bundling_p") (const_int 0)))
"(1b_0m_bs, 1b_m_cont) \
| (1b_0mi_bs, 1b_mi_cont) \