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Re: Performance regression
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Dale Johannesen <dalej at apple dot com>
- Cc: Richard Henderson <rth at redhat dot com>, gcc-patches at gcc dot gnu dot org
- Date: Mon, 30 Sep 2002 00:12:58 -0400
- Subject: Re: Performance regression
FYI, so far I have tracked the bug back to the cse2 pass. cse2 is
deleting ZERO_EXTENDs of the register representing the array slot
repeatedly written and read. With the ZERO_EXTEND only occurring once at
the beginning of the function, life_analysis is deleting the intermediary
instructions as dead.
Before cse2 the RTL looks like:
(insn 181 180 182 0 30038ec0 (set (reg:SI 156)
(zero_extend:SI (reg/v:HI 171))) -1 (nil)
(expr_list:REG_EQUAL (zero_extend:SI (mem:HI (plus:SI (reg:SI 133)
(symbol_ref:SI ("bndpsd"))) [4 S2 A16]))
(nil)))
(insn 197 196 198 0 30038ec0 (set (reg:SI 159)
(plus:SI (reg:SI 156)
(reg:SI 158))) -1 (nil)
(nil))
(insn 198 197 199 0 30038ec0 (set (reg/v:SI 154)
(sign_extend:SI (subreg:HI (reg:SI 159) 2))) -1 (nil)
(nil))
(insn 199 198 200 0 30038e40 (set (reg/v:HI 171)
(subreg:HI (reg/v:SI 154) 2)) -1 (nil)
(nil))
*REPEAT*
After cse2, the first unrolled iteration looks like that and the
remaining continue to use (reg:SI 156) without updating it from
(reg/v:HI 171) .
David