patches applioed to sh.h & sh.c

[Joern Rennecke <joern dot rennecke at superh dot com>]

Regression tested on sh-elf / sh64-elf.

-- 
--------------------------
SuperH (UK) Ltd.
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330
Wed Aug 28 15:35:17 2002  J"orn Rennecke <joern.rennecke@superh.com>

	* sh.c (calc_live_regs): Save FPSCR_REG in an interrupt handler
	if it is ever live.

	* sh.c (sh_handle_interrupt_handler_attribute): Reject interrupt_handler
	attribute for SHCOMPACT.

	* sh.h (OVERRIDE_OPTIONS): If align_function isn't set, set it
	appropriately.
	(FUNCTION_BOUNDARY): Specify only the minimum alignment required
	by the ABI.

	* sh.h (SH5_WOULD_BE_PARTIAL_NREGS): Also handle TImode case.

Index: config/sh/sh.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.c,v
retrieving revision 1.170
diff -p -r1.170 sh.c
*** config/sh/sh.c	27 Aug 2002 15:31:02 -0000	1.170
--- config/sh/sh.c	28 Aug 2002 17:37:07 -0000
*************** calc_live_regs (count_ptr, live_regs_mas
*** 4440,4446 ****
  		  && pr_live))
  	     && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
  	     && reg != RETURN_ADDRESS_POINTER_REGNUM
! 	     && reg != T_REG && reg != GBR_REG && reg != FPSCR_REG)
  	  : (/* Only push those regs which are used and need to be saved.  */
  	     regs_ever_live[reg] && ! call_used_regs[reg]))
  	{
--- 4440,4446 ----
  		  && pr_live))
  	     && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
  	     && reg != RETURN_ADDRESS_POINTER_REGNUM
! 	     && reg != T_REG && reg != GBR_REG)
  	  : (/* Only push those regs which are used and need to be saved.  */
  	     regs_ever_live[reg] && ! call_used_regs[reg]))
  	{
*************** sh_handle_interrupt_handler_attribute (n
*** 5675,5680 ****
--- 5675,5685 ----
      {
        warning ("`%s' attribute only applies to functions",
  	       IDENTIFIER_POINTER (name));
+       *no_add_attrs = true;
+     }
+   else if (TARGET_SHCOMPACT)
+     {
+       error ("attribute interrupt_handler is not compatible with -m5-compact");
        *no_add_attrs = true;
      }
  
Index: config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.167
diff -p -r1.167 sh.h
*** config/sh/sh.h	27 Aug 2002 13:05:08 -0000	1.167
--- config/sh/sh.h	28 Aug 2002 17:37:07 -0000
*************** do {									\
*** 472,477 ****
--- 472,485 ----
       break global alloc, and generates slower code anyway due		\
       to the pressure on R0.  */						\
    flag_schedule_insns = 0;						\
+ 									\
+   /* Allocation boundary (in *bits*) for the code of a function.	\
+      SH1: 32 bit alignment is faster, because instructions are always	\
+      fetched as a pair from a longword boundary.			\
+      SH2 .. SH5 : align to cache line start.  */			\
+   if (align_functions == 0)						\
+     align_functions							\
+       = TARGET_SMALLCODE ? FUNCTION_BOUNDARY : (1 << CACHE_LOG) * 8;	\
  } while (0)
  
  /* Target machine storage layout.  */
*************** do {									\
*** 532,542 ****
     The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
  #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
  
! /* Allocation boundary (in *bits*) for the code of a function.
!    32 bit alignment is faster, because instructions are always fetched as a
!    pair from a longword boundary.  */
! #define FUNCTION_BOUNDARY  \
!   (TARGET_SMALLCODE ? 16 << TARGET_SHMEDIA : (1 << CACHE_LOG) * 8)
  
  /* On SH5, the lowest bit is used to indicate SHmedia functions, so
     the vbit must go into the delta field of
--- 540,548 ----
     The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
  #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
  
! /* ABI given & required minimum allocation boundary (in *bits*) for the
!    code of a function.  */
! #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
  
  /* On SH5, the lowest bit is used to indicate SHmedia functions, so
     the vbit must go into the delta field of
*************** struct sh_args {
*** 2018,2024 ****
     : 0)
  
  #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
!   (TARGET_SH5 && (MODE) == BLKmode				\
     && ((CUM).arg_count[(int) SH_ARG_INT]			\
         + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
  
--- 2024,2030 ----
     : 0)
  
  #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
!   (TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode)	\
     && ((CUM).arg_count[(int) SH_ARG_INT]			\
         + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))