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[path] e500 varargs
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: dje at watson dot ibm dot com, gcc-patches at gcc dot gnu dot org
- Date: Fri, 26 Jul 2002 17:36:14 -0700
- Subject: [path] e500 varargs
This is the e500 varargs implementation for vectors.
Vector unnamed arguments are passed in two consecutive registers, like
long longs. If we get to r10 and need to pass an unnamed vector
argument, the vector gets put on the stack (not r10 + stack). So
vectors in the ... area get treated exactly like long longs.
Tested on powerpc-eabispe.
Ok?
Aldy
* rs6000.c (function_arg_advance): SPE vararg vectors are split
into two registers.
(function_arg): Same.
* optabs.c (expand_vector_binop): Call simplify_gen_subreg if op
is a register.
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.349
diff -c -p -r1.349 rs6000.c
*** config/rs6000/rs6000.c 26 Jul 2002 23:46:47 -0000 1.349
--- config/rs6000/rs6000.c 27 Jul 2002 00:14:33 -0000
*************** function_arg_advance (cum, mode, type, n
*** 2918,2928 ****
else
cum->words += RS6000_ARG_SIZE (mode, type);
}
! else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
! {
! cum->words += RS6000_ARG_SIZE (mode, type);
! cum->sysv_gregno++;
! }
else if (DEFAULT_ABI == ABI_V4)
{
if (TARGET_HARD_FLOAT && TARGET_FPRS
--- 2918,2926 ----
else
cum->words += RS6000_ARG_SIZE (mode, type);
}
! else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
! && named && cum->sysv_gregno <= GP_ARG_MAX_REG)
! cum->sysv_gregno++;
else if (DEFAULT_ABI == ABI_V4)
{
if (TARGET_HARD_FLOAT && TARGET_FPRS
*************** function_arg_advance (cum, mode, type, n
*** 2949,2959 ****
else
n_words = RS6000_ARG_SIZE (mode, type);
! /* Long long is put in odd registers. */
if (n_words == 2 && (gregno & 1) == 0)
gregno += 1;
! /* Long long is not split between registers and stack. */
if (gregno + n_words - 1 > GP_ARG_MAX_REG)
{
/* Long long is aligned on the stack. */
--- 2947,2958 ----
else
n_words = RS6000_ARG_SIZE (mode, type);
! /* Long long and SPE vectors are put in odd registers. */
if (n_words == 2 && (gregno & 1) == 0)
gregno += 1;
! /* Long long and SPE vectors are not split between registers
! and stack. */
if (gregno + n_words - 1 > GP_ARG_MAX_REG)
{
/* Long long is aligned on the stack. */
*************** function_arg (cum, mode, type, named)
*** 3062,3070 ****
else
return NULL;
}
! else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
{
! if (cum->sysv_gregno - 1 <= GP_ARG_MAX_REG)
return gen_rtx_REG (mode, cum->sysv_gregno);
else
return NULL;
--- 3061,3069 ----
else
return NULL;
}
! else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) && named)
{
! if (cum->sysv_gregno <= GP_ARG_MAX_REG)
return gen_rtx_REG (mode, cum->sysv_gregno);
else
return NULL;
*************** function_arg (cum, mode, type, named)
*** 3091,3103 ****
else
n_words = RS6000_ARG_SIZE (mode, type);
! /* Long long is put in odd registers. */
if (n_words == 2 && (gregno & 1) == 0)
gregno += 1;
! /* Long long is not split between registers and stack. */
if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
! return gen_rtx_REG (mode, gregno);
else
return NULL;
}
--- 3090,3118 ----
else
n_words = RS6000_ARG_SIZE (mode, type);
! /* Long long and SPE vectors are put in odd registers. */
if (n_words == 2 && (gregno & 1) == 0)
gregno += 1;
! /* Long long and SPE vectors are not split between registers
! and stack. */
if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
! {
! /* SPE vectors in ... get split into 2 registers. */
! if (TARGET_SPE && TARGET_SPE_ABI
! && SPE_VECTOR_MODE (mode) && !named)
! {
! rtx r1, r2;
! enum machine_mode m = GET_MODE_INNER (mode);
!
! r1 = gen_rtx_REG (m, gregno);
! r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
! r2 = gen_rtx_REG (m, gregno + 1);
! r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
! return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
! }
! return gen_rtx_REG (mode, gregno);
! }
else
return NULL;
}