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PowerPC64 "and" and "mask"
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: gcc-patches at gcc dot gnu dot org
- Cc: David Edelsohn <dje at watson dot ibm dot com>
- Date: Wed, 24 Jul 2002 12:36:12 +0930
- Subject: PowerPC64 "and" and "mask"
This patch allows PowerPC64 gcc to use more of the available machine
"and" type instructions, and provides a two instruction sequence for
loading a larger class of 64 bit constants. This is a slightly
cleaned up version of code that has been in use by powerpc64-linux
developers and users for months.
* config/rs6000/rs6000-protos.h (mask_operand_wrap): Declare.
(mask64_2_operand): Declare.
(build_mask64_2_operands): Declare.
(and64_2_operand): Declare.
(extract_MB): Declare.
(extract_ME): Declare.
* config/rs6000/rs6000.c (mask64_operand): Allow all ones. Remove
CONST_DOUBLE code.
(mask_operand_wrap): New insn predicate.
(mask64_2_operand): Likewise.
(and64_2_operand): Likewise.
(build_mask64_2_operands): New function.
(extract_MB): New function.
(extract_ME): New function.
(print_operand <case m,M>): Use extract_MB and extract_ME.
(print_operand <case S>): Allow all ones. Remove CONST_DOUBLE support.
* config/rs6000/rs6000.h (EXTRA_CONSTRAINT): Add 't'.
(PREDICATE_CODES): Add and64_2_operand, mask_operand_wrap and
mask64_2_operand. Remove CONST_DOUBLE from mask64_operand.
* config/rs6000/rs6000.md (andsi3_internal3): New
(andsi3_internal3+1): Enable split for powerpc64.
(andsi3_internal3+2): New split.
(andsi3_internal4): Renamed old andsi3_internal3.
(andsi3_internal5): New.
(andsi3_internal5+1): Enable split for powerpc64.
(andsi3_internal5+2): New split.
(andsi3_internal6, andsi3_internal7, andsi3_internal8): New.
(anddi3): Handle 't' constraint.
(anddi3+1): New split.
(anddi3_internal2): Handle 't' constraint.
(anddi3_internal2+1): New split.
(anddi3_internal3): Handle 't' constraint.
(anddi3_internal3+1): New split.
Some explanatory comments:
* config/rs6000/rs6000.c (mask64_operand): Allow all ones. Remove
CONST_DOUBLE code.
We need the all ones mask for build_mask64_2_operands. HOST_WIDE_INT is
always at least 64 bits, so no integer constants should appear as
CONST_DOUBLEs. More CONST_DOUBLE code can be removed from rs6000.md.
(extract_MB): New function.
(extract_ME): New function.
Code extracted from print_operand, rewritten with extra error checks,
and allowing an all ones mask. The all ones case isn't needed by gcc,
but better reflects the underlying machine insn.
(print_operand <case S>): Allow all ones. Remove CONST_DOUBLE support.
We do need the all ones case here. Code simplified.
I'm in the process of bootstrapping and regtesting powerpc-linux
mainline to ensure this doesn't break anything. Assuming all is well,
OK mainline?
--
Alan Modra
IBM OzLabs - Linux Technology Centre
diff -crp -x'*~' gcc-3.2.orig/gcc/config/rs6000/rs6000-protos.h gcc-3.2/gcc/config/rs6000/rs6000-protos.h
*** gcc-3.2.orig/gcc/config/rs6000/rs6000-protos.h 2002-07-17 14:21:20.000000000 +0930
--- gcc-3.2/gcc/config/rs6000/rs6000-protos.h 2002-07-24 08:25:22.000000000 +0930
*************** extern int non_add_cint_operand PARAMS (
*** 64,71 ****
--- 64,75 ----
extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode));
extern int logical_operand PARAMS ((rtx, enum machine_mode));
extern int mask_operand PARAMS ((rtx, enum machine_mode));
+ extern int mask_operand_wrap PARAMS ((rtx, enum machine_mode));
extern int mask64_operand PARAMS ((rtx, enum machine_mode));
+ extern int mask64_2_operand PARAMS ((rtx, enum machine_mode));
+ extern void build_mask64_2_operands PARAMS ((rtx, rtx *));
extern int and64_operand PARAMS ((rtx, enum machine_mode));
+ extern int and64_2_operand PARAMS ((rtx, enum machine_mode));
extern int and_operand PARAMS ((rtx, enum machine_mode));
extern int count_register_operand PARAMS ((rtx, enum machine_mode));
extern int xer_operand PARAMS ((rtx, enum machine_mode));
*************** extern int addrs_ok_for_quad_peep PARAMS
*** 98,103 ****
--- 102,109 ----
extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,
enum machine_mode, rtx));
extern int ccr_bit PARAMS ((rtx, int));
+ extern int extract_MB PARAMS ((rtx));
+ extern int extract_ME PARAMS ((rtx));
extern void print_operand PARAMS ((FILE *, rtx, int));
extern void print_operand_address PARAMS ((FILE *, rtx));
extern enum rtx_code rs6000_reverse_condition PARAMS ((enum machine_mode,
diff -crp -x'*~' gcc-3.2.orig/gcc/config/rs6000/rs6000.c gcc-3.2/gcc/config/rs6000/rs6000.c
*** gcc-3.2.orig/gcc/config/rs6000/rs6000.c 2002-07-17 17:46:23.000000000 +0930
--- gcc-3.2/gcc/config/rs6000/rs6000.c 2002-07-24 10:28:58.000000000 +0930
*************** mask_operand (op, mode)
*** 1496,1559 ****
return c == -lsb;
}
/* Return 1 if the operand is a constant that is a PowerPC64 mask.
It is if there are no more than one 1->0 or 0->1 transitions.
! Reject all ones and all zeros, since these should have been optimized
! away and confuse the making of MB and ME. */
int
mask64_operand (op, mode)
rtx op;
! enum machine_mode mode;
{
if (GET_CODE (op) == CONST_INT)
{
HOST_WIDE_INT c, lsb;
- /* We don't change the number of transitions by inverting,
- so make sure we start with the LS bit zero. */
c = INTVAL (op);
- if (c & 1)
- c = ~c;
! /* Reject all zeros or all ones. */
if (c == 0)
return 0;
/* Find the transition, and check that all bits above are 1's. */
lsb = c & -c;
return c == -lsb;
}
! else if (GET_CODE (op) == CONST_DOUBLE
! && (mode == VOIDmode || mode == DImode))
{
! HOST_WIDE_INT low, high, lsb;
! if (HOST_BITS_PER_WIDE_INT < 64)
! high = CONST_DOUBLE_HIGH (op);
! low = CONST_DOUBLE_LOW (op);
! if (low & 1)
! {
! if (HOST_BITS_PER_WIDE_INT < 64)
! high = ~high;
! low = ~low;
! }
! if (low == 0)
! {
! if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)
! return 0;
! lsb = high & -high;
! return high == -lsb;
! }
! lsb = low & -low;
! return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
}
else
! return 0;
}
/* Return 1 if the operand is either a non-special register or a constant
--- 1496,1680 ----
return c == -lsb;
}
+ /* Return 1 for the PowerPC64 rlwinm corner case. */
+
+ int
+ mask_operand_wrap (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+ {
+ HOST_WIDE_INT c, lsb;
+
+ if (GET_CODE (op) != CONST_INT)
+ return 0;
+
+ c = INTVAL (op);
+
+ if ((c & 0x80000001) != 0x80000001)
+ return 0;
+
+ c = ~c;
+ if (c == 0)
+ return 0;
+
+ lsb = c & -c;
+ c = ~c;
+ c &= -lsb;
+ lsb = c & -c;
+ return c == -lsb;
+ }
+
/* Return 1 if the operand is a constant that is a PowerPC64 mask.
It is if there are no more than one 1->0 or 0->1 transitions.
! Reject all zeros, since zero should have been optimized away and
! confuses the making of MB and ME. */
int
mask64_operand (op, mode)
rtx op;
! enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) == CONST_INT)
{
HOST_WIDE_INT c, lsb;
c = INTVAL (op);
! /* Reject all zeros. */
if (c == 0)
return 0;
+ /* We don't change the number of transitions by inverting,
+ so make sure we start with the LS bit zero. */
+ if (c & 1)
+ c = ~c;
+
/* Find the transition, and check that all bits above are 1's. */
lsb = c & -c;
return c == -lsb;
}
! return 0;
! }
!
! /* Like mask64_operand, but allow up to three transitions. This
! predicate is used by insn patterns that generate two rldicl or
! rldicr machine insns. */
!
! int
! mask64_2_operand (op, mode)
! rtx op;
! enum machine_mode mode ATTRIBUTE_UNUSED;
! {
! if (GET_CODE (op) == CONST_INT)
{
! HOST_WIDE_INT c, lsb;
! c = INTVAL (op);
! /* Disallow all zeros. */
! if (c == 0)
! return 0;
! /* We don't change the number of transitions by inverting,
! so make sure we start with the LS bit zero. */
! if (c & 1)
! c = ~c;
! /* Find the first transition. */
! lsb = c & -c;
! /* Invert to look for a second transition. */
! c = ~c;
!
! /* Erase first transition. */
! c &= -lsb;
!
! /* Find the second transition. */
! lsb = c & -c;
!
! /* Invert to look for a third transition. */
! c = ~c;
!
! /* Erase second transition. */
! c &= -lsb;
!
! /* Find the third transition (if any). */
! lsb = c & -c;
!
! /* Match if all the bits above are 1's (or c is zero). */
! return c == -lsb;
! }
! return 0;
! }
!
! /* Generates shifts and masks for a pair of rldicl or rldicr insns to
! implement ANDing by the mask IN. */
! void
! build_mask64_2_operands (in, out)
! rtx in;
! rtx *out;
! {
! #if HOST_BITS_PER_WIDE_INT >= 64
! unsigned HOST_WIDE_INT c, lsb, m1, m2;
! int shift;
!
! if (GET_CODE (in) != CONST_INT)
! abort ();
!
! c = INTVAL (in);
! if (c & 1)
! {
! /* Assume c initially something like 0x00fff000000fffff. The idea
! is to rotate the word so that the middle ^^^^^^ group of zeros
! is at the MS end and can be cleared with an rldicl mask. We then
! rotate back and clear off the MS ^^ group of zeros with a
! second rldicl. */
! c = ~c; /* c == 0xff000ffffff00000 */
! lsb = c & -c; /* lsb == 0x0000000000100000 */
! m1 = -lsb; /* m1 == 0xfffffffffff00000 */
! c = ~c; /* c == 0x00fff000000fffff */
! c &= -lsb; /* c == 0x00fff00000000000 */
! lsb = c & -c; /* lsb == 0x0000100000000000 */
! c = ~c; /* c == 0xff000fffffffffff */
! c &= -lsb; /* c == 0xff00000000000000 */
! shift = 0;
! while ((lsb >>= 1) != 0)
! shift++; /* shift == 44 on exit from loop */
! m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
! m1 = ~m1; /* m1 == 0x000000ffffffffff */
! m2 = ~c; /* m2 == 0x00ffffffffffffff */
}
else
! {
! /* Assume c initially something like 0xff000f0000000000. The idea
! is to rotate the word so that the ^^^ middle group of zeros
! is at the LS end and can be cleared with an rldicr mask. We then
! rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
! a second rldicr. */
! lsb = c & -c; /* lsb == 0x0000010000000000 */
! m2 = -lsb; /* m2 == 0xffffff0000000000 */
! c = ~c; /* c == 0x00fff0ffffffffff */
! c &= -lsb; /* c == 0x00fff00000000000 */
! lsb = c & -c; /* lsb == 0x0000100000000000 */
! c = ~c; /* c == 0xff000fffffffffff */
! c &= -lsb; /* c == 0xff00000000000000 */
! shift = 0;
! while ((lsb >>= 1) != 0)
! shift++; /* shift == 44 on exit from loop */
! m1 = ~c; /* m1 == 0x00ffffffffffffff */
! m1 >>= shift; /* m1 == 0x0000000000000fff */
! m1 = ~m1; /* m1 == 0xfffffffffffff000 */
! }
!
! /* Note that when we only have two 0->1 and 1->0 transitions, one of the
! masks will be all 1's. We are guaranteed more than one transition. */
! out[0] = GEN_INT (64 - shift);
! out[1] = GEN_INT (m1);
! out[2] = GEN_INT (shift);
! out[3] = GEN_INT (m2);
! #else
! abort ();
! #endif
}
/* Return 1 if the operand is either a non-special register or a constant
*************** and64_operand (op, mode)
*** 1570,1575 ****
--- 1691,1710 ----
return (logical_operand (op, mode) || mask64_operand (op, mode));
}
+ /* Like the above, but also match constants that can be implemented
+ with two rldicl or rldicr insns. */
+
+ int
+ and64_2_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+ {
+ if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
+ return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
+
+ return logical_operand (op, mode) || mask64_2_operand (op, mode);
+ }
+
/* Return 1 if the operand is either a non-special register or a
constant that can be used as the operand of an RS/6000 logical AND insn. */
*************** rs6000_init_machine_status ()
*** 6056,6061 ****
--- 6191,6273 ----
return ggc_alloc_cleared (sizeof (machine_function));
}
+ /* These macros test for integers and extract the low-order bits. */
+ #define INT_P(X) \
+ ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
+ && GET_MODE (X) == VOIDmode)
+
+ #define INT_LOWPART(X) \
+ (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
+
+ int
+ extract_MB (op)
+ rtx op;
+ {
+ int i;
+ unsigned long val = INT_LOWPART (op);
+
+ /* If the high bit is zero, the value is the first 1 bit we find
+ from the left. */
+ if ((val & 0x80000000) == 0)
+ {
+ if ((val & 0xffffffff) == 0)
+ abort ();
+
+ i = 1;
+ while (((val <<= 1) & 0x80000000) == 0)
+ ++i;
+ return i;
+ }
+
+ /* If the high bit is set and the low bit is not, or the mask is all
+ 1's, the value is zero. */
+ if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
+ return 0;
+
+ /* Otherwise we have a wrap-around mask. Look for the first 0 bit
+ from the right. */
+ i = 31;
+ while (((val >>= 1) & 1) != 0)
+ --i;
+
+ return i;
+ }
+
+ int
+ extract_ME (op)
+ rtx op;
+ {
+ int i;
+ unsigned long val = INT_LOWPART (op);
+
+ /* If the low bit is zero, the value is the first 1 bit we find from
+ the right. */
+ if ((val & 1) == 0)
+ {
+ if ((val & 0xffffffff) == 0)
+ abort ();
+
+ i = 30;
+ while (((val >>= 1) & 1) == 0)
+ --i;
+
+ return i;
+ }
+
+ /* If the low bit is set and the high bit is not, or the mask is all
+ 1's, the value is 31. */
+ if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
+ return 31;
+
+ /* Otherwise we have a wrap-around mask. Look for the first 0 bit
+ from the left. */
+ i = 0;
+ while (((val <<= 1) & 0x80000000) != 0)
+ ++i;
+
+ return i;
+ }
+
/* Print an operand. Recognize special options, documented below. */
#if TARGET_ELF
*************** print_operand (file, x, code)
*** 6074,6087 ****
{
int i;
HOST_WIDE_INT val;
!
! /* These macros test for integers and extract the low-order bits. */
! #define INT_P(X) \
! ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
! && GET_MODE (X) == VOIDmode)
!
! #define INT_LOWPART(X) \
! (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
switch (code)
{
--- 6286,6292 ----
{
int i;
HOST_WIDE_INT val;
! unsigned HOST_WIDE_INT uval;
switch (code)
{
*************** print_operand (file, x, code)
*** 6297,6330 ****
if (! mask_operand (x, SImode))
output_operand_lossage ("invalid %%m value");
! val = INT_LOWPART (x);
!
! /* If the high bit is set and the low bit is not, the value is zero.
! If the high bit is zero, the value is the first 1 bit we find from
! the left. */
! if ((val & 0x80000000) && ((val & 1) == 0))
! {
! putc ('0', file);
! return;
! }
! else if ((val & 0x80000000) == 0)
! {
! for (i = 1; i < 32; i++)
! if ((val <<= 1) & 0x80000000)
! break;
! fprintf (file, "%d", i);
! return;
! }
!
! /* Otherwise, look for the first 0 bit from the right. The result is its
! number plus 1. We know the low-order bit is one. */
! for (i = 0; i < 32; i++)
! if (((val >>= 1) & 1) == 0)
! break;
!
! /* If we ended in ...01, i would be 0. The correct value is 31, so
! we want 31 - i. */
! fprintf (file, "%d", 31 - i);
return;
case 'M':
--- 6502,6508 ----
if (! mask_operand (x, SImode))
output_operand_lossage ("invalid %%m value");
! fprintf (file, "%d", extract_MB (x));
return;
case 'M':
*************** print_operand (file, x, code)
*** 6332,6366 ****
if (! mask_operand (x, SImode))
output_operand_lossage ("invalid %%M value");
! val = INT_LOWPART (x);
!
! /* If the low bit is set and the high bit is not, the value is 31.
! If the low bit is zero, the value is the first 1 bit we find from
! the right. */
! if ((val & 1) && ((val & 0x80000000) == 0))
! {
! fputs ("31", file);
! return;
! }
! else if ((val & 1) == 0)
! {
! for (i = 0; i < 32; i++)
! if ((val >>= 1) & 1)
! break;
!
! /* If we had ....10, i would be 0. The result should be
! 30, so we need 30 - i. */
! fprintf (file, "%d", 30 - i);
! return;
! }
!
! /* Otherwise, look for the first 0 bit from the left. The result is its
! number minus 1. We know the high-order bit is one. */
! for (i = 0; i < 32; i++)
! if (((val <<= 1) & 0x80000000) == 0)
! break;
!
! fprintf (file, "%d", i);
return;
/* %n outputs the negative of its operand. */
--- 6510,6516 ----
if (! mask_operand (x, SImode))
output_operand_lossage ("invalid %%M value");
! fprintf (file, "%d", extract_ME (x));
return;
/* %n outputs the negative of its operand. */
*************** print_operand (file, x, code)
*** 6456,6523 ****
return;
case 'S':
! /* PowerPC64 mask position. All 0's and all 1's are excluded.
CONST_INT 32-bit mask is considered sign-extended so any
transition must occur within the CONST_INT, not on the boundary. */
if (! mask64_operand (x, DImode))
output_operand_lossage ("invalid %%S value");
! val = INT_LOWPART (x);
! if (val & 1) /* Clear Left */
{
! for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
! if (!((val >>= 1) & 1))
! break;
!
! #if HOST_BITS_PER_WIDE_INT == 32
! if (GET_CODE (x) == CONST_DOUBLE && i == 32)
! {
! val = CONST_DOUBLE_HIGH (x);
!
! if (val == 0)
! --i;
! else
! for (i = 32; i < 64; i++)
! if (!((val >>= 1) & 1))
! break;
! }
! #endif
! /* i = index of last set bit from right
! mask begins at 63 - i from left */
! if (i > 63)
! output_operand_lossage ("%%S computed all 1's mask");
!
! fprintf (file, "%d", 63 - i);
! return;
}
! else /* Clear Right */
{
! for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
! if ((val >>= 1) & 1)
! break;
!
! #if HOST_BITS_PER_WIDE_INT == 32
! if (GET_CODE (x) == CONST_DOUBLE && i == 32)
! {
! val = CONST_DOUBLE_HIGH (x);
!
! if (val == (HOST_WIDE_INT) -1)
! --i;
! else
! for (i = 32; i < 64; i++)
! if ((val >>= 1) & 1)
! break;
! }
! #endif
! /* i = index of last clear bit from right
! mask ends at 62 - i from left */
! if (i > 62)
! output_operand_lossage ("%%S computed all 0's mask");
!
! fprintf (file, "%d", 62 - i);
! return;
}
case 'T':
/* Print the symbolic name of a branch target register. */
--- 6606,6636 ----
return;
case 'S':
! /* PowerPC64 mask position. All 0's is excluded.
CONST_INT 32-bit mask is considered sign-extended so any
transition must occur within the CONST_INT, not on the boundary. */
if (! mask64_operand (x, DImode))
output_operand_lossage ("invalid %%S value");
! uval = INT_LOWPART (x);
! if (uval & 1) /* Clear Left */
{
! uval &= ((unsigned HOST_WIDE_INT) 1 << 63 << 1) - 1;
! i = 64;
}
! else /* Clear Right */
{
! uval = ~uval;
! uval &= ((unsigned HOST_WIDE_INT) 1 << 63 << 1) - 1;
! i = 63;
}
+ while (uval != 0)
+ --i, uval >>= 1;
+ if (i < 0)
+ abort ();
+ fprintf (file, "%d", i);
+ return;
case 'T':
/* Print the symbolic name of a branch target register. */
diff -crp -x'*~' gcc-3.2.orig/gcc/config/rs6000/rs6000.h gcc-3.2/gcc/config/rs6000/rs6000.h
*** gcc-3.2.orig/gcc/config/rs6000/rs6000.h 2002-07-17 14:21:20.000000000 +0930
--- gcc-3.2/gcc/config/rs6000/rs6000.h 2002-07-24 09:24:53.000000000 +0930
*************** enum reg_class
*** 1178,1184 ****
'R' is for AIX TOC entries.
'S' is a constant that can be placed into a 64-bit mask operand
'T' is a constant that can be placed into a 32-bit mask operand
! 'U' is for V.4 small data references. */
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
--- 1178,1185 ----
'R' is for AIX TOC entries.
'S' is a constant that can be placed into a 64-bit mask operand
'T' is a constant that can be placed into a 32-bit mask operand
! 'U' is for V.4 small data references.
! 't' is for AND masks that can be performed by two rldic{l,r} insns. */
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
*************** enum reg_class
*** 1187,1192 ****
--- 1188,1197 ----
: (C) == 'T' ? mask_operand (OP, SImode) \
: (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
&& small_data_operand (OP, GET_MODE (OP))) \
+ : (C) == 't' ? (mask64_2_operand (OP, DImode) \
+ && (fixed_regs[CR0_REGNO] \
+ || !logical_operand (OP, DImode)) \
+ && !mask64_operand (OP, DImode)) \
: 0)
/* Given an rtx X being reloaded into a reg required to be
*************** extern char rs6000_reg_names[][8]; /* re
*** 2749,2758 ****
{"non_add_cint_operand", {CONST_INT}}, \
{"and_operand", {SUBREG, REG, CONST_INT}}, \
{"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
{"mask_operand", {CONST_INT}}, \
! {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
{"count_register_operand", {REG}}, \
{"xer_operand", {REG}}, \
{"symbol_ref_operand", {SYMBOL_REF}}, \
--- 2754,2766 ----
{"non_add_cint_operand", {CONST_INT}}, \
{"and_operand", {SUBREG, REG, CONST_INT}}, \
{"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
+ {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
{"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
{"mask_operand", {CONST_INT}}, \
! {"mask_operand_wrap", {CONST_INT}}, \
! {"mask64_operand", {CONST_INT}}, \
! {"mask64_2_operand", {CONST_INT}}, \
{"count_register_operand", {REG}}, \
{"xer_operand", {REG}}, \
{"symbol_ref_operand", {SYMBOL_REF}}, \
diff -crp -x'*~' gcc-3.2.orig/gcc/config/rs6000/rs6000.md gcc-3.2/gcc/config/rs6000/rs6000.md
*** gcc-3.2.orig/gcc/config/rs6000/rs6000.md 2002-07-21 13:49:13.000000000 +0930
--- gcc-3.2/gcc/config/rs6000/rs6000.md 2002-07-24 08:50:06.000000000 +0930
***************
*** 2885,2891 ****
{andiu.|andis.} %0,%1,%u2")
;; Note to set cr's other than cr0 we do the and immediate and then
! ;; the test again -- this avoids a mcrf which on the higher end
;; machines causes an execution serialization
(define_insn "*andsi3_internal2"
--- 2885,2891 ----
{andiu.|andis.} %0,%1,%u2")
;; Note to set cr's other than cr0 we do the and immediate and then
! ;; the test again -- this avoids a mfcr which on the higher end
;; machines causes an execution serialization
(define_insn "*andsi3_internal2"
***************
*** 2908,2913 ****
--- 2908,2933 ----
[(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,8,8,8,8")])
+ (define_insn "*andsi3_internal3"
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
+ (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
+ (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+ (const_int 0)))
+ (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
+ (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
+ "TARGET_POWERPC64"
+ "@
+ #
+ {andil.|andi.} %3,%1,%b2
+ {andiu.|andis.} %3,%1,%u2
+ {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
+ #
+ #
+ #
+ #"
+ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
+ (set_attr "length" "8,4,4,4,8,8,8,8")])
+
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
***************
*** 2915,2921 ****
(const_int 0)))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:CC 4 ""))]
! "! TARGET_POWERPC64 && reload_completed"
[(parallel [(set (match_dup 3)
(and:SI (match_dup 1)
(match_dup 2)))
--- 2935,2941 ----
(const_int 0)))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:CC 4 ""))]
! "reload_completed"
[(parallel [(set (match_dup 3)
(and:SI (match_dup 1)
(match_dup 2)))
***************
*** 2925,2931 ****
(const_int 0)))]
"")
! (define_insn "*andsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
(match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
--- 2945,2971 ----
(const_int 0)))]
"")
! ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
! ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
!
! (define_split
! [(set (match_operand:CC 0 "cc_reg_operand" "")
! (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "gpc_reg_operand" ""))
! (const_int 0)))
! (clobber (match_scratch:SI 3 ""))
! (clobber (match_scratch:CC 4 ""))]
! "TARGET_POWERPC64 && reload_completed"
! [(parallel [(set (match_dup 3)
! (and:SI (match_dup 1)
! (match_dup 2)))
! (clobber (match_dup 4))])
! (set (match_dup 0)
! (compare:CC (match_dup 3)
! (const_int 0)))]
! "")
!
! (define_insn "*andsi3_internal4"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
(match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
***************
*** 2947,2952 ****
--- 2987,3014 ----
[(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
(set_attr "length" "4,4,4,4,8,8,8,8")])
+ (define_insn "*andsi3_internal5"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
+ (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
+ (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
+ (and:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
+ "TARGET_POWERPC64"
+ "@
+ #
+ {andil.|andi.} %0,%1,%b2
+ {andiu.|andis.} %0,%1,%u2
+ {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
+ #
+ #
+ #
+ #"
+ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
+ (set_attr "length" "8,4,4,4,8,8,8,8")])
+
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
***************
*** 2956,2962 ****
(and:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:CC 4 ""))]
! "! TARGET_POWERPC64 && reload_completed"
[(parallel [(set (match_dup 0)
(and:SI (match_dup 1)
(match_dup 2)))
--- 3018,3043 ----
(and:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:CC 4 ""))]
! "reload_completed"
! [(parallel [(set (match_dup 0)
! (and:SI (match_dup 1)
! (match_dup 2)))
! (clobber (match_dup 4))])
! (set (match_dup 3)
! (compare:CC (match_dup 0)
! (const_int 0)))]
! "")
!
! (define_split
! [(set (match_operand:CC 3 "cc_reg_operand" "")
! (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
! (match_operand:SI 2 "gpc_reg_operand" ""))
! (const_int 0)))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (and:SI (match_dup 1)
! (match_dup 2)))
! (clobber (match_scratch:CC 4 ""))]
! "TARGET_POWERPC64 && reload_completed"
[(parallel [(set (match_dup 0)
(and:SI (match_dup 1)
(match_dup 2)))
***************
*** 2966,2971 ****
--- 3047,3131 ----
(const_int 0)))]
"")
+ ;; Handle the PowerPC64 rlwinm corner case
+
+ (define_insn_and_split "*andsi3_internal6"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "mask_operand_wrap" "i")))]
+ "TARGET_POWERPC64"
+ "#"
+ "TARGET_POWERPC64"
+ [(set (match_dup 0)
+ (and:SI (rotate:SI (match_dup 1) (match_dup 3))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (rotate:SI (match_dup 0) (match_dup 5)))]
+ "
+ {
+ int mb = extract_MB (operands[2]);
+ int me = extract_ME (operands[2]);
+ operands[3] = GEN_INT (me + 1);
+ operands[5] = GEN_INT (32 - (me + 1));
+ operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
+ }"
+ [(set_attr "length" "8")])
+
+ (define_insn_and_split "*andsi3_internal7"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
+ (match_operand:SI 1 "mask_operand_wrap" "i,i"))
+ (const_int 0)))
+ (clobber (match_scratch:SI 3 "=r,r"))]
+ "TARGET_POWERPC64"
+ "#"
+ "TARGET_POWERPC64"
+ [(parallel [(set (match_dup 2)
+ (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
+ (match_dup 5))
+ (const_int 0)))
+ (clobber (match_dup 3))])]
+ "
+ {
+ int mb = extract_MB (operands[1]);
+ int me = extract_ME (operands[1]);
+ operands[4] = GEN_INT (me + 1);
+ operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
+ }"
+ [(set_attr "type" "delayed_compare,compare")
+ (set_attr "length" "4,8")])
+
+ (define_insn_and_split "*andsi3_internal8"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "mask_operand_wrap" "i,i"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (and:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "#"
+ "TARGET_POWERPC64"
+ [(parallel [(set (match_dup 3)
+ (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
+ (match_dup 5))
+ (const_int 0)))
+ (set (match_dup 0)
+ (and:SI (rotate:SI (match_dup 1) (match_dup 4))
+ (match_dup 5)))])
+ (set (match_dup 0)
+ (rotate:SI (match_dup 0) (match_dup 6)))]
+ "
+ {
+ int mb = extract_MB (operands[2]);
+ int me = extract_ME (operands[2]);
+ operands[4] = GEN_INT (me + 1);
+ operands[6] = GEN_INT (32 - (me + 1));
+ operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
+ }"
+ [(set_attr "type" "delayed_compare,compare")
+ (set_attr "length" "8,12")])
+
(define_expand "iorsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
***************
*** 7235,7258 ****
"")
(define_insn "anddi3"
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
! (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
! (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
! (clobber (match_scratch:CC 3 "=X,X,x,x"))]
"TARGET_POWERPC64"
"@
and %0,%1,%2
rldic%B2 %0,%1,0,%S2
andi. %0,%1,%b2
! andis. %0,%1,%u2")
(define_insn "*anddi3_internal2"
! [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
! (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,")
! (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
(const_int 0)))
! (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r"))
! (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
"TARGET_POWERPC64"
"@
and. %3,%1,%2
--- 7395,7441 ----
"")
(define_insn "anddi3"
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
! (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
! (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
! (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
"TARGET_POWERPC64"
"@
and %0,%1,%2
rldic%B2 %0,%1,0,%S2
andi. %0,%1,%b2
! andis. %0,%1,%u2
! #"
! [(set_attr "length" "4,4,4,4,8")])
!
! (define_split
! [(set (match_operand:DI 0 "gpc_reg_operand" "")
! (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
! (match_operand:DI 2 "mask64_2_operand" "")))
! (clobber (match_scratch:CC 3 ""))]
! "TARGET_POWERPC64
! && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
! && !mask64_operand (operands[2], DImode)"
! [(set (match_dup 0)
! (and:DI (rotate:DI (match_dup 1)
! (match_dup 4))
! (match_dup 5)))
! (set (match_dup 0)
! (and:DI (rotate:DI (match_dup 0)
! (match_dup 6))
! (match_dup 7)))]
! "
! {
! build_mask64_2_operands (operands[2], &operands[4]);
! }")
(define_insn "*anddi3_internal2"
! [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
! (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
! (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
(const_int 0)))
! (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
! (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"@
and. %3,%1,%2
***************
*** 7262,7270 ****
#
#
#
#"
! [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
! (set_attr "length" "4,4,4,4,8,8,8,8")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
--- 7445,7455 ----
#
#
#
+ #
+ #
#"
! [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
! (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
(define_split
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
***************
*** 7283,7296 ****
(const_int 0)))]
"")
(define_insn "*anddi3_internal3"
! [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
! (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
! (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
(const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
(and:DI (match_dup 1) (match_dup 2)))
! (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
"TARGET_POWERPC64"
"@
and. %0,%1,%2
--- 7468,7506 ----
(const_int 0)))]
"")
+ (define_split
+ [(set (match_operand:CC 0 "cc_reg_operand" "")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "mask64_2_operand" ""))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 ""))
+ (clobber (match_scratch:CC 4 ""))]
+ "TARGET_POWERPC64 && reload_completed
+ && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
+ && !mask64_operand (operands[2], DImode)"
+ [(set (match_dup 3)
+ (and:DI (rotate:DI (match_dup 1)
+ (match_dup 5))
+ (match_dup 6)))
+ (parallel [(set (match_dup 0)
+ (compare:CC (and:DI (rotate:DI (match_dup 3)
+ (match_dup 7))
+ (match_dup 8))
+ (const_int 0)))
+ (clobber (match_dup 3))])]
+ "
+ {
+ build_mask64_2_operands (operands[2], &operands[5]);
+ }")
+
(define_insn "*anddi3_internal3"
! [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
! (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
! (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
(const_int 0)))
! (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
(and:DI (match_dup 1) (match_dup 2)))
! (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
"TARGET_POWERPC64"
"@
and. %0,%1,%2
***************
*** 7300,7308 ****
#
#
#
#"
! [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
! (set_attr "length" "4,4,4,4,8,8,8,8")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
--- 7510,7520 ----
#
#
#
+ #
+ #
#"
! [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
! (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
(define_split
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
***************
*** 7321,7326 ****
--- 7533,7567 ----
(const_int 0)))]
"")
+ (define_split
+ [(set (match_operand:CC 3 "cc_reg_operand" "")
+ (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
+ (match_operand:DI 2 "mask64_2_operand" ""))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "")
+ (and:DI (match_dup 1) (match_dup 2)))
+ (clobber (match_scratch:CC 4 ""))]
+ "TARGET_POWERPC64 && reload_completed
+ && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
+ && !mask64_operand (operands[2], DImode)"
+ [(set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 1)
+ (match_dup 5))
+ (match_dup 6)))
+ (parallel [(set (match_dup 3)
+ (compare:CC (and:DI (rotate:DI (match_dup 0)
+ (match_dup 7))
+ (match_dup 8))
+ (const_int 0)))
+ (set (match_dup 0)
+ (and:DI (rotate:DI (match_dup 0)
+ (match_dup 7))
+ (match_dup 8)))])]
+ "
+ {
+ build_mask64_2_operands (operands[2], &operands[5]);
+ }")
+
(define_expand "iordi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")