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Re: 4 GCC regressions, 2 new, with your patch on 2002-07-18T09:56:17Z.


> > With your recent patch, GCC has some regression test failures, which
> > used to pass.  There are 2 new failures, and 2
> > failures that existed before and after that patch; 0 failures
> > have been fixed.
> > 
> > The new failures are:
> > powerpc-eabisim gcc.sum gcc.dg/20010822-1.c
> > native gcc.sum gcc.dg/20010822-1.c
> 
> I guess I would have to conclude that these are mines however strange it
> looks.  I will check what is going on.

Hi,
this is another interesting problem. What happends is that code hoisting
(insert_insn_end_bb) inserts load in between flags set and conditional
jump instruction. This is valid, since load does not clobber flags, but
not very sane as we lose optimizaiton opurtunities.

However, the code gets wrong in ifcvt as ifcvt insert new code before
the flags set and uses uninitialized register.

This patch fixes the gcse part by avoiding code hoisting to insert
instructions as such a crazy places.  I believe this is good thing to
do, but still I would like to know what to do with ifcvt.

Regtested bootstrapped mainline.  I am now rerunning bootstrap with -Os.
OK for mainline?

Honza

Mon Jul 22 03:02:47 CEST 2002  Jan Hubicka  <jh@suse.cz>
	* gcse.c (insert_insn_end_bb): Do not insert in between flags setter
	and user.
Index: gcse.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/gcse.c,v
retrieving revision 1.211
diff -c -3 -p -r1.211 gcse.c
*** gcse.c	21 Jul 2002 19:38:08 -0000	1.211
--- gcse.c	22 Jul 2002 01:02:44 -0000
*************** insert_insn_end_bb (expr, bb, pre)
*** 4970,4975 ****
--- 4970,4977 ----
  #ifdef HAVE_cc0
        rtx note;
  #endif
+       rtx set_insn, set;
+ 
        /* It should always be the case that we can put these instructions
  	 anywhere in the basic block with performing PRE optimizations.
  	 Check this.  */
*************** insert_insn_end_bb (expr, bb, pre)
*** 5000,5005 ****
--- 5002,5016 ----
  	    insn = maybe_cc0_setter;
  	}
  #endif
+       /* We don't want to put instruction in between flag set and flag use
+          even when flags are represented as hard register.  */
+       set_insn = prev_nonnote_insn (insn);
+       if (GET_CODE (set_insn) == INSN
+ 	  && (set = single_set (set_insn)) != 0
+ 	  && REG_P (SET_DEST (set))
+ 	  && REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER
+ 	  && !reg_overlap_mentioned_p (SET_DEST (set), pat))
+ 	insn = set_insn;
        /* FIXME: What if something in cc0/jump uses value set in new insn?  */
        new_insn = emit_insn_before (pat, insn);
      }


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