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Updated ns32k port patches
Ian Dall writes:
> I guess I am on the wrong branch.
> [...]
> I'll synchronize and resubmit.
Here is the revised ChangeLog entry:
2002-07-13 Ian Dall <ian@sibyl.beware.dropbear.id.au>
* doc/invoke.texi (NS32K Options): Document -mieee-fp option
* config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
into addsi3 using register class "x" and "y".
* config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
"earlyclobber" constraint modifier for some alternative.
* config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
(*ble, *blt): Flag to indicate bCOND and sCOND should check for
unordered.
config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.
* config/ns32k/ns32k.h (TARGET_IEEE_FP, MASK_IEEE_FP)
(TARGET_SWITCHES): Add -mieee-fp option.
(OVERRIDE_OPTIONS): 32332 is a subset of
32532. Don't use IEEE_FP -funsafe-math-optimizations.
(TARGET_SWITCHES): Fix description of bitfield option.
* config/ns32k/netbsd.h (TARGET_DEFAULT): Add
-mieee-fp option. Remove 32332 flag.
And here is the patch:
Index: doc/invoke.texi
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.1.1.3
retrieving revision 1.3
diff -c -r1.1.1.3 -r1.3
*** doc/invoke.texi 14 Jul 2002 12:28:22 -0000 1.1.1.3
--- doc/invoke.texi 14 Jul 2002 15:00:17 -0000 1.3
***************
*** 8693,8698 ****
--- 8693,8707 ----
Generate output containing library calls for floating point.
@strong{Warning:} the requisite libraries may not be available.
+ @item -mieee-fp
+ @itemx -mno-ieee-fp
+ @opindex mieee-fp
+ @opindex mno-ieee-fp
+ Control whether or not the compiler uses IEEE floating point
+ comparisons. These handle correctly the case where the result of a
+ comparison is unordered.
+ @strong{Warning:} the requisite kernel support may not be available.
+
@item -mnobitfield
@opindex mnobitfield
Do not use the bit-field instructions. On some machines it is faster to
Index: config/ns32k/netbsd.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/netbsd.h,v
retrieving revision 1.1.1.3
retrieving revision 1.3
diff -c -r1.1.1.3 -r1.3
*** config/ns32k/netbsd.h 14 Jul 2002 12:23:51 -0000 1.1.1.3
--- config/ns32k/netbsd.h 14 Jul 2002 15:00:05 -0000 1.3
***************
*** 34,42 ****
FPU is 32381;
Use multiply-add instructions */
#define TARGET_DEFAULT \
! (MASK_32532|MASK_32332 | MASK_NO_SB | MASK_NO_BITFIELD | \
! MASK_32081|MASK_32381 | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
--- 34,43 ----
FPU is 32381;
Use multiply-add instructions */
+ #undef TARGET_DEFAULT
#define TARGET_DEFAULT \
! (MASK_32532 | MASK_NO_SB | MASK_NO_BITFIELD | \
! MASK_32381 | MASK_IEEE_FP | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
Index: config/ns32k/ns32k.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.h,v
retrieving revision 1.1.1.4
diff -c -r1.1.1.4 ns32k.h
*** config/ns32k/ns32k.h 14 Jul 2002 12:23:52 -0000 1.1.1.4
--- config/ns32k/ns32k.h 15 Jul 2002 12:05:16 -0000
***************
*** 82,87 ****
--- 82,88 ----
extern int target_flags;
+ /* Masks for target_flags */
#define MASK_32081 1
#define MASK_RTD 2
#define MASK_REGPARM 4
***************
*** 93,98 ****
--- 94,100 ----
#define MASK_32381 256
#define MASK_MULT_ADD 512
#define MASK_SRC 1024
+ #define MASK_IEEE_FP 2048
/* Macros used in the machine description to test the flags. */
***************
*** 121,137 ****
/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
#define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
-
#define TARGET_SWITCHES \
{ { "32081", MASK_32081, N_("Use hardware fp")}, \
{ "soft-float", -(MASK_32081|MASK_32381), \
--- 123,141 ----
/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
+
#define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
+ #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "32081", MASK_32081, N_("Use hardware fp")}, \
{ "soft-float", -(MASK_32081|MASK_32381), \
***************
*** 148,164 ****
N_("Register sb is zero. Use for absolute addressing")}, \
{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
{ "bitfield", -MASK_NO_BITFIELD, \
N_("Do not use bit-field instructions")}, \
- { "nobitfield", MASK_NO_BITFIELD, N_("Use bit-field instructions")},\
{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
{ "32381", MASK_32381, N_("32381 fpu")}, \
{ "mult-add", MASK_MULT_ADD, \
N_("Use multiply-accumulate fp instructions")}, \
{ "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
--- 152,172 ----
N_("Register sb is zero. Use for absolute addressing")}, \
{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
{ "bitfield", -MASK_NO_BITFIELD, \
+ N_("Use bit-field instructions")}, \
+ { "nobitfield", MASK_NO_BITFIELD, \
N_("Do not use bit-field instructions")}, \
{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
{ "32381", MASK_32381, N_("32381 fpu")}, \
{ "mult-add", MASK_MULT_ADD, \
N_("Use multiply-accumulate fp instructions")}, \
{ "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
+ { "ieee-fp", MASK_IEEE_FP, N_("Use IEEE math for fp comparisons")}, \
+ { "noieee-fp", -MASK_IEEE_FP, \
+ N_("Do not use IEEE math for fp comparisons")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
***************
*** 166,179 ****
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (flag_pic || TARGET_HIMEM) \
! target_flags |= MASK_NO_SB; \
! if (TARGET_32381) \
! target_flags |= MASK_32081; \
! else \
! target_flags &= ~MASK_MULT_ADD; \
}
/* Zero or more C statements that may conditionally modify two
--- 174,191 ----
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (target_flags & MASK_32532) \
! target_flags |= MASK_32332; \
! if (flag_pic || TARGET_HIMEM) \
! target_flags |= MASK_NO_SB; \
! if (TARGET_32381) \
! target_flags |= MASK_32081; \
! else \
! target_flags &= ~MASK_MULT_ADD; \
! if (flag_unsafe_math_optimizations) \
! target_flags &= ~MASK_IEEE_FP; \
}
/* Zero or more C statements that may conditionally modify two
***************
*** 1179,1184 ****
--- 1191,1200 ----
/* This bit means that what ought to be in the Z bit
is complemented in the F bit. */
#define CC_Z_IN_NOT_F 010000
+
+ /* This bit means that the L bit indicates unordered (IEEE) comparison.
+ */
+ #define CC_UNORD 020000
/* Store in cc_status the expressions
that the condition codes will describe
Index: config/ns32k/ns32k.md
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.md,v
retrieving revision 1.1.1.3
retrieving revision 1.4
diff -c -r1.1.1.3 -r1.4
*** config/ns32k/ns32k.md 14 Jul 2002 12:23:52 -0000 1.1.1.3
--- config/ns32k/ns32k.md 13 Jul 2002 13:56:36 -0000 1.4
***************
*** 94,99 ****
--- 94,101 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_FP)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (DFmode);
return \"cmpl %1,%0\"; }")
***************
*** 103,108 ****
--- 105,112 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_FP)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (SFmode);
return \"cmpf %1,%0\"; }")
***************
*** 202,215 ****
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "cmpl %0,%1")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "cmpf %0,%1")
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
--- 206,227 ----
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_FP)
! cc_status.flags |= CC_UNORD;
! return \"cmpl %0,%1\";}")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_FP)
! cc_status.flags |= CC_UNORD;
! return \"cmpf %0,%1\";}")
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
***************
*** 798,804 ****
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
--- 810,816 ----
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
***************
*** 809,815 ****
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
--- 821,827 ----
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
***************
*** 822,828 ****
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
--- 834,840 ----
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
***************
*** 832,838 ****
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
--- 844,850 ----
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
***************
*** 883,902 ****
return \"adjspd %n0\";
}")
- (define_insn "*frame_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 24)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(fp),%0")
-
- (define_insn "*stack_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 25)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(sp),%0")
-
(define_insn "adddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(plus:DI (match_operand:DI 1 "general_operand" "%0")
--- 895,900 ----
***************
*** 940,948 ****
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
! (match_operand:SI 2 "general_operand" "g,i")))]
""
"*
{
--- 938,946 ----
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
! (match_operand:SI 2 "general_operand" "g,i,i")))]
""
"*
{
***************
*** 964,969 ****
--- 962,975 ----
return \"addr %c2(%1),%0\";
}
}
+ else if (which_alternative == 2)
+ {
+ if (GET_CODE (operands[2]) == CONST_INT &&
+ NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
+ return \"addr %c2(%1),%0\";
+ else
+ return \"sprd %1,%0\;addd %2,%0\";
+ }
else if (GET_CODE (operands[2]) == CONST_INT)
{
int i = INTVAL (operands[2]);
***************
*** 2313,2319 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "blt %l0")
(define_insn "bltu"
[(set (pc)
--- 2319,2331 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "bltu"
[(set (pc)
***************
*** 2349,2355 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "ble %l0")
(define_insn "bleu"
[(set (pc)
--- 2361,2373 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "bleu"
[(set (pc)
***************
*** 2399,2405 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "ble %l0")
(define_insn "*bleu"
[(set (pc)
--- 2417,2429 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "*bleu"
[(set (pc)
***************
*** 2435,2441 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "blt %l0")
(define_insn "*bltu"
[(set (pc)
--- 2459,2471 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "*bltu"
[(set (pc)