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Re: [RFC] PowerPC DFA description
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Vladimir Makarov <vmakarov at redhat dot com>
- Cc: Jeffrey Law <law at redhat dot com>, dalej at apple dot com, Daniel Berlin <dan at dberlin dot org>, gcc-patches at gcc dot gnu dot org
- Date: Thu, 06 Jun 2002 18:53:01 -0400
- Subject: Re: [RFC] PowerPC DFA description
>>>>> Vladimir Makarov writes:
Vlad> You are absolutely
Vlad> correctly understand the DFA syntax. It looks like incorrect
Vlad> description of the processor. You also propose the right solution
Vlad> (replacing mciu_iter by mciu).
I have rearranged the DFA descriptions into a separate file for
each group of similar processors, like the other GCC architectures which
have been converted.
I performed a comparison of some benchmarks compiled for PPC604e
processor with the corrected DFA description, with the corrected DFA
description removing dispatch modeling, with the original scheduling
description. (The DFA description without modeling the dispatch unit
should be equivalent to a direct translation of the original scheduling
description to DFA language.)
The results are: original description best, DFA translation 1%
slower, DFA with dispatch 3-4% slower.
Why does one need to model dispatch if issue rate is specified? I
can understand modeling dispatch for Altivec on PPC7450 where only two
instructions can get dispatched to four sub-units per cycle, but general
dispatch modeling seems redundant. I don't see that modeled for other
DFA descriptions contributed to GCC.
Thanks, David