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Re: AMD Athlon DFA description
> > Hi,
> > the attached patch implements DFA scheduling for AMD Athlon.
> > Once I stabilize the CFG branch, I will install it there so it will
> > get benchmarked for SPEC benchmark. I will send incremental patch
> > for pentium shortly.
> Hi,
> sadly the testing has shown about 1 point (0.2%) performance degradation due to
> the patch, so I will try another round before sending for mainline approval.
Hi,
this patch fixes few bogus things in the Athlon descrition, but I doubt
it is the purpose of degradation.
I think there are two major problems in the new model
Firstly, the ieu unit is modeled as nothing. In case I uncomment:
;(define_cpu_unit "athlon-ieu0" "athlon_ieu")
;(define_cpu_unit "athlon-ieu1" "athlon_ieu")
;(define_cpu_unit "athlon-ieu2" "athlon_ieu")
;(define_reservation "athlon-ieu" "(athlon-ieu0 | athlon-ieu1 | athlon-ieu2)")
The size of automata runs out of control, since ieu has both low latency
stuf and very high latency stuff. Any idea what to do here?
Overcommiting of ieu unit for div/mul may be purpose of slowdown (partly).
In the simple testcases I have, the imul/idiv instructions are always
present.
Other bogus model is the FP fmul pipe. It has latency of 3 but supports
long latency operations. This is done by cycling mulitple upos over the pipe,
so for instance fdiv consume the unit for multiple cycles, but at each
n*3+1, n*3+2 cycles new insturctions can be accepted.
If I model this using (fmul, nothing, nothing)*10, I again run out of
control.
In the old scheduler I was modeling it as 3 nonpipelined units that
ensured that the pipe won't get overcommited and on-chip scheduler
took care to make everything fit. BUt I would expect to run into
similar explosion as for athlon-ieu units.
Better ideas?
Honza
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.325.2.14
diff -c -3 -p -r1.325.2.14 i386.md
*** i386.md 4 May 2002 11:23:57 -0000 1.325.2.14
--- i386.md 5 May 2002 12:24:50 -0000
***************
*** 856,862 ****
;; communicates with all the execution units separately instead.
(define_attr "athlon_decode" "direct,vector"
! (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
(const_string "vector")
(and (eq_attr "type" "push")
(match_operand 1 "memory_operand" ""))
--- 856,862 ----
;; communicates with all the execution units separately instead.
(define_attr "athlon_decode" "direct,vector"
! (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld")
(const_string "vector")
(and (eq_attr "type" "push")
(match_operand 1 "memory_operand" ""))
***************
*** 904,917 ****
;(define_cpu_unit "athlon-agu1" "athlon_agu")
;(define_cpu_unit "athlon-agu2" "athlon_agu")
;(define_reservation "athlon-agu" "(athlon-agu0 | athlon-agu1 | athlon-agu2)")
! (define_reservation "athlon-agu" "nothing")
(define_cpu_unit "athlon-mult" "athlon_mult")
(define_cpu_unit "athlon-load0" "athlon")
(define_cpu_unit "athlon-load1" "athlon")
(define_reservation "athlon-load" "athlon-agu,
- nothing,
(athlon-load0 | athlon-load1)")
(define_reservation "athlon-store" "nothing")
--- 904,916 ----
;(define_cpu_unit "athlon-agu1" "athlon_agu")
;(define_cpu_unit "athlon-agu2" "athlon_agu")
;(define_reservation "athlon-agu" "(athlon-agu0 | athlon-agu1 | athlon-agu2)")
! (define_reservation "athlon-agu" "nothing,nothing")
(define_cpu_unit "athlon-mult" "athlon_mult")
(define_cpu_unit "athlon-load0" "athlon")
(define_cpu_unit "athlon-load1" "athlon")
(define_reservation "athlon-load" "athlon-agu,
(athlon-load0 | athlon-load1)")
(define_reservation "athlon-store" "nothing")
***************
*** 932,938 ****
(define_insn_reservation "athlon_pop" 4
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "push"))
! "athlon-direct,athlon-ieu,athlon-load")
(define_insn_reservation "athlon_leave" 3
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "push"))
--- 931,937 ----
(define_insn_reservation "athlon_pop" 4
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "push"))
! "athlon-vector,athlon-ieu,athlon-load")
(define_insn_reservation "athlon_leave" 3
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "push"))
***************
*** 942,977 ****
(define_insn_reservation "athlon_lea" 2
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "lea"))
! "athlon-direct,athlon-agu,nothing")
;; Mul executes in special multiplier unit attached to IEU0
(define_insn_reservation "athlon_imul" 5
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "imul")
(eq_attr "memory" "none")))
! "athlon-vector,athlon-ieu+athlon-mult,nothing,nothing,athlon-ieu")
(define_insn_reservation "athlon_imul_mem" 8
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "imul")
(eq_attr "memory" "load,both")))
! "athlon-direct,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu")
(define_insn_reservation "athlon_idiv" 42
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "idiv")
(eq_attr "memory" "none")))
! "athlon-direct,athlon-ieu,athlon-mult*41")
(define_insn_reservation "athlon_idiv_mem" 45
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "idiv")
(eq_attr "memory" "load,both")))
! "athlon-direct,athlon-load,athlon-ieu,athlon-mult*41")
(define_insn_reservation "athlon_str" 15
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "str")
! (eq_attr "memory" "load,both")))
! "athlon-direct,athlon-load,athlon-ieu,athlon-mult*10")
!
!
(define_insn_reservation "athlon_idirect" 1
(and (eq_attr "cpu" "athlon")
--- 941,974 ----
(define_insn_reservation "athlon_lea" 2
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "lea"))
! "athlon-direct,athlon-agu")
;; Mul executes in special multiplier unit attached to IEU0
(define_insn_reservation "athlon_imul" 5
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "imul")
(eq_attr "memory" "none")))
! "athlon-vector,athlon-ieu+athlon-mult,nothing,nothing,nothing,athlon-ieu")
(define_insn_reservation "athlon_imul_mem" 8
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "imul")
(eq_attr "memory" "load,both")))
! "athlon-vector,athlon-load,athlon-ieu+athlon-mult,nothing,nothing,nothing,athlon-ieu")
(define_insn_reservation "athlon_idiv" 42
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "idiv")
(eq_attr "memory" "none")))
! "athlon-vector,athlon-ieu*42")
(define_insn_reservation "athlon_idiv_mem" 45
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "idiv")
(eq_attr "memory" "load,both")))
! "athlon-vector,athlon-load,athlon-ieu*42")
(define_insn_reservation "athlon_str" 15
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "str")
! (eq_attr "memory" "load,both,store")))
! "athlon-vector,athlon-load,athlon-ieu*10")
(define_insn_reservation "athlon_idirect" 1
(and (eq_attr "cpu" "athlon")
***************
*** 1006,1012 ****
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "imov")
(eq_attr "memory" "store")))
! "athlon-direct,athlon-store")
(define_insn_reservation "athlon_idirect_both" 4
(and (eq_attr "cpu" "athlon")
(and (eq_attr "athlon_decode" "direct")
--- 1003,1009 ----
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "imov")
(eq_attr "memory" "store")))
! "athlon-direct,athlon-agu,athlon-store")
(define_insn_reservation "athlon_idirect_both" 4
(and (eq_attr "cpu" "athlon")
(and (eq_attr "athlon_decode" "direct")
***************
*** 1102,1112 ****
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "fpspc")
(eq_attr "memory" "load")))
! "athlon-direct,athlon-load,athlon-fmul")
(define_insn_reservation "athlon_fpspc" 100
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "fpspc"))
! "athlon-direct,athlon-fmul")
(define_insn_reservation "athlon_fcmov_load" 10
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "fcmov")
--- 1099,1109 ----
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "fpspc")
(eq_attr "memory" "load")))
! "athlon-vector,athlon-load,athlon-fmul")
(define_insn_reservation "athlon_fpspc" 100
(and (eq_attr "cpu" "athlon")
(eq_attr "type" "fpspc"))
! "athlon-vector,athlon-fmul")
(define_insn_reservation "athlon_fcmov_load" 10
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "fcmov")