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rs6000 tweaks
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 01 May 2002 12:57:18 -0400
- Subject: rs6000 tweaks
* rs6000.md (abssi2_nopower): Convert to define_insn_and_split.
(nabs_nopower): Same.
(floatdisf2): New pattern.
(absdi2): Convert to define_insn_and_split.
(nabsdi2): Same.
(trunctfsf2): Same.
(floatditf2): Same.
(floatsitf2): Same.
(fix_trunctfdi2): Same.
(fix_trunctfsi2): Same.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.182
diff -c -p -r1.182 rs6000.md
*** rs6000.md 28 Apr 2002 20:26:54 -0000 1.182
--- rs6000.md 30 Apr 2002 22:26:38 -0000
***************
*** 2114,2143 ****
}
}")
! (define_insn "abssi2_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER"
"abs %0,%1")
! (define_insn "abssi2_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
! (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER"
! "*
! {
! return (TARGET_POWERPC)
! ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
! : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
! }"
! [(set_attr "length" "12")])
!
! (define_split
! [(set (match_operand:SI 0 "gpc_reg_operand" "")
! (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
! (clobber (match_scratch:SI 2 ""))]
! "! TARGET_POWER && reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
--- 2114,2132 ----
}
}")
! (define_insn "*abssi2_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER"
"abs %0,%1")
! (define_insn_and_split "abssi2_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
! (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER"
! "#"
! "&& reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
***************
*** 2149,2172 ****
"TARGET_POWER"
"nabs %0,%1")
! (define_insn "*nabs_no_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
! (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER"
! "*
! {
! return (TARGET_POWERPC)
! ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
! : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
! }"
! [(set_attr "length" "12")])
!
! (define_split
! [(set (match_operand:SI 0 "gpc_reg_operand" "")
! (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))))
! (clobber (match_scratch:SI 2 ""))]
! "! TARGET_POWER && reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
--- 2138,2150 ----
"TARGET_POWER"
"nabs %0,%1")
! (define_insn_and_split "*nabs_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
! (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER"
! "#"
! "&& reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
***************
*** 5462,5467 ****
--- 5440,5459 ----
"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fctidz %0,%1"
[(set_attr "type" "fp")])
+
+ ;; This only is safe if rounding mode set appropriately.
+ (define_insn_and_split "floatdisf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
+ (clobber (match_scratch:DF 2 "=f"))]
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (float:DF (match_dup 1)))
+ (set (match_dup 0)
+ (float_truncate:SF (match_dup 2)))]
+ "")
;; Define the DImode operations that can be done in a small number
;; of instructions. The & constraints are to prevent the register
***************
*** 6070,6106 ****
}
}")
! (define_insn "absdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
! (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64"
! "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
! [(set_attr "length" "12")])
!
! (define_split
! [(set (match_operand:DI 0 "gpc_reg_operand" "")
! (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
! (clobber (match_scratch:DI 2 ""))]
! "TARGET_POWERPC64 && reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
"")
! (define_insn "*nabsdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
! (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64"
! "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
! [(set_attr "length" "12")])
!
! (define_split
! [(set (match_operand:DI 0 "gpc_reg_operand" "")
! (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))))
! (clobber (match_scratch:DI 2 ""))]
! "TARGET_POWERPC64 && reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
--- 6062,6086 ----
}
}")
! (define_insn_and_split "absdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
! (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64"
! "#"
! "&& reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
"")
! (define_insn_and_split "*nabsdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
! (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64"
! "#"
! "&& reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
***************
*** 8207,8258 ****
(define_insn_and_split "trunctfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
! ""
[(set (match_dup 2)
(float_truncate:DF (match_dup 1)))
(set (match_dup 0)
(float_truncate:SF (match_dup 2)))]
! "
! {
! operands[2] = gen_reg_rtx (DFmode);
! }")
! (define_expand "floatditf2"
[(set (match_dup 2)
(float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))]
! "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
! && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "{ operands[2] = gen_reg_rtx (DFmode); }")
! (define_expand "floatsitf2"
[(set (match_dup 2)
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))]
! "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "{ operands[2] = gen_reg_rtx (DFmode); }")
! (define_expand "fix_trunctfdi2"
[(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))]
! "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
! && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "{ operands[2] = gen_reg_rtx (DFmode); }")
! (define_expand "fix_trunctfsi2"
[(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))]
! "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "{ operands[2] = gen_reg_rtx (DFmode); }")
(define_insn "negtf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
--- 8187,8254 ----
(define_insn_and_split "trunctfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
! (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
! (clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
! "&& reload_completed"
[(set (match_dup 2)
(float_truncate:DF (match_dup 1)))
(set (match_dup 0)
(float_truncate:SF (match_dup 2)))]
! "")
! (define_insn_and_split "floatditf2"
! [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
! (float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
! (clobber (match_scratch:DF 2 "=f"))]
! "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
! && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "#"
! "&& reload_completed"
[(set (match_dup 2)
(float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))]
! "")
! (define_insn_and_split "floatsitf2"
! [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
! (float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
! (clobber (match_scratch:DF 2 "=f"))]
! "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "#"
! "&& reload_completed"
[(set (match_dup 2)
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))]
! "")
! (define_insn_and_split "fix_trunctfdi2"
! [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
! (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
! "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
! && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "#"
! "&& reload_completed"
[(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))]
! "")
! (define_insn_and_split "fix_trunctfsi2"
! [(set (match_operand:SI 0 "gpc_reg_operand" "=f")
! (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
! "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
! "#"
! "&& reload_completed"
[(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))]
! "")
(define_insn "negtf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")