Index: gcc/config/rs6000/rs6000.md
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.170.2.6
diff -u -p -r1.170.2.6 rs6000.md
--- gcc/config/rs6000/rs6000.md	26 Apr 2002 18:22:51 -0000	1.170.2.6
+++ gcc/config/rs6000/rs6000.md	28 Apr 2002 14:08:58 -0000
@@ -11394,13 +11409,12 @@
    (set_attr "length" "12,16")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
 	(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
   "! TARGET_POWERPC64"
-  "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
+  "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
   [(set_attr "length" "8")])
 
 (define_insn ""
@@ -11732,15 +11746,14 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
 	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+		 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
   "! TARGET_POWERPC64"
   "@
-  {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-  {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
+  {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
+  {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
  [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12041,15 +12054,14 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
 	(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
   "! TARGET_POWERPC64"
   "@
-   {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
-   {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
+   {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
+   {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
   [(set_attr "length" "8")])
 
 (define_insn ""
@@ -12342,13 +12354,12 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
 	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(const_int 0))
-		 (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&r"))]
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))]
   "! TARGET_POWERPC64"
-  "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
+  "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12678,15 +12689,14 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
 	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
-		 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+		 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
   "! TARGET_POWERPC64"
   "@
-   {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
+   {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
+   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
   [(set_attr "length" "8,12")])
 
 (define_insn ""