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Re: Gcc 3.1 performance regressions with respect to 2.95.3


	The status of my LIBCALL / SCHED_GROUP_P patch is: SCHED_GROUP_P
fixes the LIBCALL problem; sched2 ICEd because SCHED_GROUP_P was left set
from the sched1, clearing SCHED_GROUP_P after use fixed that.  The
remaining problem is that sched-rgn.c:schedule_insns() dies in
CHECK_DEAD_NOTES. 

	My analysis of this ICE is that either GCC is generating bogus RTL
to begin with or the test is bogus.  The problem is that GCC produces code
like the appended output (emit-rtl.i.19.regmove).  The important pieces to
notice are that reg:DI 124 is first created in a LIBCALL clobber, then
used in another LIBCALL for reg:DI 180 during which reg:DI 124 dies, then
reg:DI 124 reappears with a *bare* clobber that is not part of a LIBCALL
and dies again.  These multiple occurances of reg:DI 124 appear in the
initial RTL.

	SCHED_GROUP_P is attached to clobbers associated with LIBCALLs,
not free-standing clobbers.  The scheduler issue_rate change to avoid
counting pseudo-instructions (e.g., clobbers) allows the clobber to be
scheduled at the beginning of the region.  When schedule_insns() updates
the life information, reg:DI 124 now remains live, therefore one less
register death and the count of death notes in the region no longer
matches the number before scheduling.

	Should reg:DI 124 be used twice?  Should we attach the bare
clobber to the following SET?  Is counting reg deaths a bogus self-check?
Does anyone other than The Shadow[1] know the answer to there questions? :-)

[1] The Shadow: 1930-1954 CBS radio serial

Thanks, David


;; Start of basic block 10, registers live: 1 [1] 31 [31] 67 [ap] 117
(note 1254 165 172 [bb 10] NOTE_INSN_BASIC_BLOCK)

(insn 172 1254 1356 (set (reg:SI 175)
        (ashift:SI (reg/v:SI 117)
            (const_int 2 [0x2]))) 131 {ashlsi3_no_power} (nil)
    (expr_list:REG_DEAD (reg/v:SI 117)
        (expr_list:REG_EQUAL (mult:SI (reg/v:SI 117)
                (const_int 4 [0x4]))
            (nil))))

(insn 1356 172 176 (set (reg/f:SI 452)
        (plus:SI (reg/f:SI 31 r31 [116])
            (const_int 168 [0xa8]))) 36 {*addsi3_internal1} (nil)
    (expr_list:REG_EQUAL (plus:SI (reg/f:SI 31 r31 [116])
            (const_int 168 [0xa8]))
        (nil)))

(insn 176 1356 181 (set (reg:SI 177)
        (mem:SI (plus:SI (reg:SI 175)
                (reg/f:SI 452)) [23 k S4 A32])) 299 {*movsi_internal1} (insn_lis
t 172 (insn_list 1356 (nil)))
    (expr_list:REG_DEAD (reg:SI 175)
        (expr_list:REG_DEAD (reg/f:SI 452)
            (nil))))

(note 181 176 184 NOTE_INSN_DELETED)

(insn 184 181 177 (clobber (reg/v:DI 124)) -1 (nil)
    (insn_list:REG_LIBCALL 186 (nil)))

(insn 177 184 183 (set (subreg:SI (reg/v:DI 124) 4)
        (reg:SI 177)) 299 {*movsi_internal1} (insn_list 176 (insn_list 184 (nil)
))
    (nil))

(insn 183 177 186 (set (subreg:SI (reg/v:DI 124) 0)
        (ashiftrt:SI (reg:SI 177)
            (const_int 31 [0x1f]))) 158 {ashrsi3_no_power} (insn_list 177 (nil))
    (expr_list:REG_DEAD (reg:SI 177)
        (nil)))

(insn 186 183 192 (set (reg/v:DI 124)
        (reg/v:DI 124)) 318 {*movdi_internal32} (insn_list 183 (nil))
    (insn_list:REG_RETVAL 184 (expr_list:REG_EQUAL (sign_extend:DI (mem:SI (plus
:SI (reg:SI 175)
                        (reg/f:SI 452)) [23 k S4 A32]))
            (nil))))

(insn 192 186 188 (clobber (reg:DI 180)) -1 (nil)
    (insn_list:REG_LIBCALL 194 (nil)))

(insn 188 192 191 (set (subreg:SI (reg:DI 180) 0)
        (const_int 0 [0x0])) 299 {*movsi_internal1} (insn_list 192 (nil))
    (expr_list:REG_NO_CONFLICT (reg/v:DI 124)

        (nil)))

(insn 191 188 194 (set (subreg:SI (reg:DI 180) 4)
        (subreg:SI (reg/v:DI 124) 4)) 299 {*movsi_internal1} (insn_list 186 (ins
n_list 188 (nil)))
    (expr_list:REG_DEAD (reg/v:DI 124)
        (expr_list:REG_NO_CONFLICT (reg/v:DI 124)
            (nil))))

(insn 194 191 199 (set (reg:DI 180)
        (reg:DI 180)) 318 {*movdi_internal32} (insn_list 191 (nil))
    (insn_list:REG_RETVAL 192 (expr_list:REG_EQUAL (and:DI (reg/v:DI 124)
                (const_int 4294967295 [0xffffffff]))
            (nil))))

(insn 199 194 196 (clobber (reg:DI 182)) -1 (nil)
    (insn_list:REG_LIBCALL 201 (nil)))

(insn 196 199 198 (set (subreg:SI (reg:DI 182) 0)
        (subreg:SI (reg:DI 180) 0)) 299 {*movsi_internal1} (insn_list 194 (insn_
list 199 (nil)))
    (expr_list:REG_NO_CONFLICT (reg:DI 180)
        (nil)))

(insn 198 196 201 (set (subreg:SI (reg:DI 182) 4)
        (xor:SI (subreg:SI (reg:DI 180) 4)
            (const_int -2147483648 [0xffffffff80000000]))) 89 {*boolsi3_internal
1} (insn_list 196 (nil))
    (expr_list:REG_DEAD (reg:DI 180)
        (expr_list:REG_NO_CONFLICT (reg:DI 180)
            (nil))))

(insn 201 198 204 (set (reg:DI 182)
        (reg:DI 182)) 318 {*movdi_internal32} (insn_list 198 (nil))
    (insn_list:REG_RETVAL 199 (expr_list:REG_EQUAL (xor:DI (reg:DI 180)
                (const_int 2147483648 [0x80000000]))
            (nil))))

(insn 204 201 206 (clobber (reg/v:DI 124)) -1 (nil)
    (nil))

(insn 206 204 207 (set (subreg:SI (reg/v:DI 124) 4)
        (plus:SI (subreg:SI (reg:DI 182) 4)
            (const_int -2147483648 [0xffffffff80000000]))) 36 {*addsi3_internal1
} (insn_list 201 (insn_list 204 (nil)))
    (nil))

(note 207 206 208 NOTE_INSN_DELETED)

(insn 208 207 210 (set (reg:SI 185)
        (ltu:SI (subreg:SI (reg/v:DI 124) 4)
            (subreg:SI (reg:DI 182) 4))) 436 {*rs6000.md:11929} (insn_list 206 (
nil))
    (nil))

(insn 210 208 212 (set (subreg:SI (reg/v:DI 124) 0)
        (plus:SI (subreg:SI (reg:DI 182) 0)
            (const_int -1 [0xffffffffffffffff]))) 36 {*addsi3_internal1} (nil)
    (expr_list:REG_DEAD (reg:DI 182)
        (nil)))

(note 212 210 214 NOTE_INSN_DELETED)

(insn 214 212 221 (set (subreg:SI (reg/v:DI 124) 0)
        (plus:SI (reg:SI 185)
            (subreg:SI (reg/v:DI 124) 0))) 36 {*addsi3_internal1} (insn_list 210
 (insn_list 208 (nil)))
    (expr_list:REG_DEAD (reg:SI 185)
        (nil)))

(insn 221 214 223 (set (reg:SI 3 r3)
        (const_int 0 [0x0])) 299 {*movsi_internal1} (nil)
    (expr_list:REG_EQUAL (const_int 0 [0x0])
        (nil)))

(insn 223 221 224 (set (reg:DI 4 r4)
        (reg/v:DI 124)) 318 {*movdi_internal32} (insn_list 214 (nil))
    (expr_list:REG_DEAD (reg/v:DI 124)
        (nil)))

(call_insn 224 223 226 (parallel[ 
            (set (reg:SI 3 r3)
                (call (mem:SI (symbol_ref/v:SI ("gen_rtx_CONST_INT")) [0 S4 A8])
                    (const_int 32 [0x20])))
            (use (const_int 0 [0x0]))
            (clobber (scratch:SI))
        ] ) 369 {*call_value_local32} (insn_list 221 (insn_list 223 (nil)))
    (expr_list:REG_DEAD (reg:DI 4 r4)
        (expr_list:REG_UNUSED (scratch:SI)
            (expr_list:REG_EH_REGION (const_int 0 [0x0])
                (nil))))
    (expr_list (use (reg:DI 4 r4))
        (expr_list (use (reg:SI 3 r3))
            (nil))))

(insn 226 224 229 (set (reg/f:SI 115)
        (reg:SI 3 r3)) 299 {*movsi_internal1} (insn_list 224 (nil))
    (expr_list:REG_DEAD (reg:SI 3 r3)
        (nil)))

(jump_insn 229 226 230 (set (pc)
        (label_ref 1234)) 497 {jump} (nil)
    (nil))
;; End of basic block 10, registers live:
 1 [1] 31 [31] 67 [ap] 115


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