Re: [PATCH] Fold zero extensions into bit-wise ANDs

[Roger Sayle <roger at eyesopen dot com>]

Hi Richard,
> It's probably not an optimization if sizeof(x) <= sizeof(word_mode)
> and sizeof(T) > sizeof(word_mode) regardless of the sign.  Which
> you are not currently checking, so I won't approve this patch.

These are exactly the cases that can (and should) be handled by an
architecture's .md file.  Consider the code "x & 1" where sizeof(x) >
sizeof(word_mode).   If this operation is best performed by two machine
instructions, that's how they should be emitted by the RTL expander.
The expander should test whether the high bits beyond the low word are
all zero, and a  zero_extend, xor or mov to zero it.

Forgive the x86 assembler syntax, but something like turning the
instruction "andw %ax,$1" into the sequence:

	andb %al, $1
	xorb %ah, %ah


Additionally, representing these as single wide instructions in the
RTL allows more optimizations in the backend, including CSE and GCSE.
c.f. the issues with HISUM and LOSUM (sp?)


As an excellent counter example, consider

long long foo(unsigned char bar)
{
  return bar & 0x24;
}

with the current mainline CVS we'd generate:

foo:	movzbl	4(%esp), %ecx
	xorl	%edx, %edx
	andb	$36, %cl
	movzbl	%cl, %eax
	ret

with my patch applied it now generates

foo:	movzbl	4(%esp), %eax
	andl	$36, %eax
	cltd
	ret

which by my reckoning is shorter, faster and uses less registers.


If you can find any cases where my patch produces worse code, I'm
more than happy to investigate further.  In the mean-time, the SPEC
CPU2000 improvements and the concrete examples in my posts indicate
that we're generating better code than we did before.

Roger
--
Roger Sayle,                         E-mail: roger@eyesopen.com
OpenEye Scientific Software,         WWW: http://www.eyesopen.com/
Suite 1107, 3600 Cerrillos Road,     Tel: (+1) 505-473-7385
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