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mips16 x mips_isa
- From: Alexandre Oliva <aoliva at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 05 Apr 2002 06:09:09 -0300
- Subject: mips16 x mips_isa
- Organization: GCC Team, Red Hat
When configuring for say mipsisa32-elf, or any other mips target whose
MIPS_DEFAULT_ISA was an ISA that contained instructions not present in
the mips16 ISA, we'd sometimes generate invalid instructions as if
they were present in the mips16 ISA. This patch fixes these
problems. I'm checking it in, approved by Eric Christopher. Tested
with athlon-pc-linux-gnu-x-mipsisa32-elf.
Index: gcc/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* config/mips/mips.h (ISA_HAS_BRANCHLIKELY, ISA_HAS_CONDMOVE,
ISA_HAS_FP4, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB,
ISA_HAS_CLZ_CLO, ISA_HAS_DCLZ_DCLO): Disable if TARGET_MIPS16.
Index: gcc/config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/mips/mips.h,v
retrieving revision 1.175
diff -u -p -r1.175 mips.h
--- gcc/config/mips/mips.h 2002/04/05 08:00:30 1.175
+++ gcc/config/mips/mips.h 2002/04/05 09:06:12
@@ -634,52 +634,51 @@ extern void sbss_section PARAMS ((void)
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
- /* || TARGET_MIPS3900 */)
+ && ! TARGET_MIPS16)
/* ISA has the conditional move instructions introduced in mips4. */
-#define ISA_HAS_CONDMOVE (mips_isa == 4 \
- || mips_isa == 32 \
- || mips_isa == 64)
+#define ISA_HAS_CONDMOVE ((mips_isa == 4 \
+ || mips_isa == 32 \
+ || mips_isa == 64) \
+ && ! TARGET_MIPS16)
/* ISA has just the integer condition move instructions (movn,movz) */
#define ISA_HAS_INT_CONDMOVE 0
-
-
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (mips_isa == 4 \
|| mips_isa == 32 \
|| mips_isa == 64)
-
/* This is a catch all for the other new mips4 instructions: indexed load and
indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
and the FP recip and recip sqrt instructions */
#define ISA_HAS_FP4 (mips_isa == 4 \
- )
+ && ! TARGET_MIPS16)
/* ISA has conditional trap instructions. */
-#define ISA_HAS_COND_TRAP (mips_isa >= 2 && ! TARGET_MIPS16)
+#define ISA_HAS_COND_TRAP (mips_isa >= 2 \
+ && ! TARGET_MIPS16)
/* ISA has multiply-accumulate instructions, madd and msub. */
-#define ISA_HAS_MADD_MSUB (mips_isa == 32 \
- || mips_isa == 64 \
- )
+#define ISA_HAS_MADD_MSUB ((mips_isa == 32 \
+ || mips_isa == 64 \
+ ) && ! TARGET_MIPS16)
/* ISA has nmadd and nmsub instructions. */
#define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
- )
+ && ! TARGET_MIPS16)
/* ISA has count leading zeroes/ones instruction (not implemented). */
-#define ISA_HAS_CLZ_CLO (mips_isa == 32 \
- || mips_isa == 64 \
- )
+#define ISA_HAS_CLZ_CLO ((mips_isa == 32 \
+ || mips_isa == 64 \
+ ) && ! TARGET_MIPS16)
/* ISA has double-word count leading zeroes/ones instruction (not
implemented). */
-#define ISA_HAS_DCLZ_DCLO (mips_isa == 64)
-
+#define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \
+ && ! TARGET_MIPS16)
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer