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kill sparc -mno-epilogue
- From: Richard Henderson <rth at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sat, 30 Mar 2002 19:15:09 -0800
- Subject: kill sparc -mno-epilogue
This code has bit-rotten and doesn't actually work anymore. Jakub sez
that the last time he benchmarked things, -mepilogue (the default) was
faster anyway.
PR target/5352 complains about the bad code generation that results.
Thus doesn't "fix" it so much as emphaticly say "don't do that".
r~
* config/sparc/sparc.c: Remove all references to TARGET_EPILOGUE.
(sparc_emitting_epilogue): New.
(leaf_label, output_return, sparc_return_peephole_ok): Remove.
* config/sparc/sparc-protos.h: Update.
* config/sparc/sparc.h (MASK_EPILOGUE, TARGET_EPILOGUE): Remove.
(TARGET_SWITCHES): Update.
* config/sparc/sparc.md (return): Remove.
(return_*): Use sparc_emitting_epilogue, not !TARGET_EPILOGUE.
* config/sparc/freebsd.h, config/sparc/linux64.h, config/sparc/lite.h,
config/sparc/liteelf.h, config/sparc/netbsd-elf.h,
config/sparc/sol2-sld-64.h, config/sparc/sol2.h,
config/sparc/sp64-aout.h, config/sparc/sp64-elf.h,
config/sparc/sp86x-aout.h, config/sparc/sp86x-elf.h,
config/sparc/splet.h, config/sparc/vxsparc64.h (TARGET_DEFAULT):
Remove MASK_EPILOGUE.
* doc/invoke.texi: Update.
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.119.2.8
diff -c -p -d -r1.119.2.8 invoke.texi
*** doc/invoke.texi 2002/03/29 23:21:40 1.119.2.8
--- doc/invoke.texi 2002/03/31 03:01:32
*************** in the following sections.
*** 348,357 ****
-mcmodel=@var{code-model} @gol
-m32 -m64 @gol
-mapp-regs -mbroken-saverestore -mcypress @gol
! -mepilogue -mfaster-structs -mflat @gol
-mfpu -mhard-float -mhard-quad-float @gol
-mimpure-text -mlive-g0 -mno-app-regs @gol
! -mno-epilogue -mno-faster-structs -mno-flat -mno-fpu @gol
-mno-impure-text -mno-stack-bias -mno-unaligned-doubles @gol
-msoft-float -msoft-quad-float -msparclite -mstack-bias @gol
-msupersparc -munaligned-doubles -mv8}
--- 348,357 ----
-mcmodel=@var{code-model} @gol
-m32 -m64 @gol
-mapp-regs -mbroken-saverestore -mcypress @gol
! -mfaster-structs -mflat @gol
-mfpu -mhard-float -mhard-quad-float @gol
-mimpure-text -mlive-g0 -mno-app-regs @gol
! -mno-faster-structs -mno-flat -mno-fpu @gol
-mno-impure-text -mno-stack-bias -mno-unaligned-doubles @gol
-msoft-float -msoft-quad-float -msparclite -mstack-bias @gol
-msupersparc -munaligned-doubles -mv8}
*************** a trap handler for one of these instruct
*** 5209,5226 ****
emulates the effect of the instruction. Because of the trap handler overhead,
this is much slower than calling the ABI library routines. Thus the
@option{-msoft-quad-float} option is the default.
-
- @item -mno-epilogue
- @itemx -mepilogue
- @opindex mno-epilogue
- @opindex mepilogue
- With @option{-mepilogue} (the default), the compiler always emits code for
- function exit at the end of each function. Any function exit in
- the middle of the function (such as a return statement in C) will
- generate a jump to the exit code at the end of the function.
-
- With @option{-mno-epilogue}, the compiler tries to emit exit code inline
- at every function exit.
@item -mno-flat
@itemx -mflat
--- 5209,5214 ----
Index: config/sparc/freebsd.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/freebsd.h,v
retrieving revision 1.3.4.3
diff -c -p -d -r1.3.4.3 freebsd.h
*** config/sparc/freebsd.h 2002/03/29 05:22:32 1.3.4.3
--- config/sparc/freebsd.h 2002/03/31 03:01:32
*************** the Free Software Foundation, 675 Mass A
*** 92,98 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_64BIT + MASK_PTR64 /* + MASK_FASTER_STRUCTS */ \
! + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU \
+ MASK_LONG_DOUBLE_128 /* + MASK_HARD_QUAD */)
/* The default code model. */
--- 92,98 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_64BIT + MASK_PTR64 /* + MASK_FASTER_STRUCTS */ \
! + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU \
+ MASK_LONG_DOUBLE_128 /* + MASK_HARD_QUAD */)
/* The default code model. */
Index: config/sparc/linux64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/linux64.h,v
retrieving revision 1.44.8.2
diff -c -p -d -r1.44.8.2 linux64.h
*** config/sparc/linux64.h 2002/03/27 10:28:15 1.44.8.2
--- config/sparc/linux64.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 34,40 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
! + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
#undef ASM_CPU_DEFAULT_SPEC
--- 34,40 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
! + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
#undef ASM_CPU_DEFAULT_SPEC
Index: config/sparc/lite.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/lite.h,v
retrieving revision 1.4
diff -c -p -d -r1.4 lite.h
*** config/sparc/lite.h 2001/11/12 23:52:28 1.4
--- config/sparc/lite.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 28,34 ****
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
/* US Software GOFAST library support. */
#undef INIT_SUBTARGET_OPTABS
--- 28,34 ----
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT MASK_APP_REGS
/* US Software GOFAST library support. */
#undef INIT_SUBTARGET_OPTABS
Index: config/sparc/liteelf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/liteelf.h,v
retrieving revision 1.7
diff -c -p -d -r1.7 liteelf.h
*** config/sparc/liteelf.h 2001/12/16 15:40:58 1.7
--- config/sparc/liteelf.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 38,44 ****
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
/* US Software GOFAST library support. */
#undef INIT_SUBTARGET_OPTABS
--- 38,44 ----
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT MASK_APP_REGS
/* US Software GOFAST library support. */
#undef INIT_SUBTARGET_OPTABS
Index: config/sparc/netbsd-elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/netbsd-elf.h,v
retrieving revision 1.1.6.1
diff -c -p -d -r1.1.6.1 netbsd-elf.h
*** config/sparc/netbsd-elf.h 2002/03/27 10:28:15 1.1.6.1
--- config/sparc/netbsd-elf.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 137,144 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
! + MASK_STACK_BIAS + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU \
! + MASK_LONG_DOUBLE_128)
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDANY
--- 137,143 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
! + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_MEDANY
Index: config/sparc/sol2-sld-64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sol2-sld-64.h,v
retrieving revision 1.21
diff -c -p -d -r1.21 sol2-sld-64.h
*** config/sparc/sol2-sld-64.h 2002/02/01 19:30:01 1.21
--- config/sparc/sol2-sld-64.h 2002/03/31 03:01:32
***************
*** 27,33 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
! MASK_STACK_BIAS + MASK_EPILOGUE + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
/* The default code model. */
--- 27,33 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ + \
! MASK_STACK_BIAS + MASK_FPU + MASK_LONG_DOUBLE_128)
#endif
/* The default code model. */
Index: config/sparc/sol2.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sol2.h,v
retrieving revision 1.36.2.3
diff -c -p -d -r1.36.2.3 sol2.h
*** config/sparc/sol2.h 2002/03/27 10:28:16 1.36.2.3
--- config/sparc/sol2.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 239,245 ****
/* Solaris allows 64 bit out and global registers in 32 bit mode.
sparc_override_options will disable V8+ if not generating V9 code. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_EPILOGUE + MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128)
/*
* Attempt to turn on access permissions for the stack.
--- 239,245 ----
/* Solaris allows 64 bit out and global registers in 32 bit mode.
sparc_override_options will disable V8+ if not generating V9 code. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128)
/*
* Attempt to turn on access permissions for the stack.
Index: config/sparc/sp64-aout.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sp64-aout.h,v
retrieving revision 1.7
diff -c -p -d -r1.7 sp64-aout.h
*** config/sparc/sp64-aout.h 2001/11/14 21:44:20 1.7
--- config/sparc/sp64-aout.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 26,32 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
! + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS)
/* The only code model supported is Medium/Low. */
#undef SPARC_DEFAULT_CMODEL
--- 26,32 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
! + MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS)
/* The only code model supported is Medium/Low. */
#undef SPARC_DEFAULT_CMODEL
Index: config/sparc/sp64-elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sp64-elf.h,v
retrieving revision 1.21
diff -c -p -d -r1.21 sp64-elf.h
*** config/sparc/sp64-elf.h 2001/12/17 15:05:39 1.21
--- config/sparc/sp64-elf.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 33,39 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
! + MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
--- 33,39 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
! + MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
#undef SPARC_DEFAULT_CMODEL
#define SPARC_DEFAULT_CMODEL CM_EMBMEDANY
Index: config/sparc/sp86x-aout.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sp86x-aout.h,v
retrieving revision 1.6
diff -c -p -d -r1.6 sp86x-aout.h
*** config/sparc/sp86x-aout.h 2001/11/12 23:52:28 1.6
--- config/sparc/sp86x-aout.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 28,34 ****
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#undef ASM_SPEC
#define ASM_SPEC "%{v:-v} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
--- 28,34 ----
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT MASK_APP_REGS
#undef ASM_SPEC
#define ASM_SPEC "%{v:-v} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
Index: config/sparc/sp86x-elf.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sp86x-elf.h,v
retrieving revision 1.8
diff -c -p -d -r1.8 sp86x-elf.h
*** config/sparc/sp86x-elf.h 2001/12/16 15:40:58 1.8
--- config/sparc/sp86x-elf.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 38,44 ****
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#undef ASM_SPEC
#define ASM_SPEC "%{v:-V} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
--- 38,44 ----
/* Enable app-regs and epilogue options. Do not enable the fpu. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT MASK_APP_REGS
#undef ASM_SPEC
#define ASM_SPEC "%{v:-V} %{mlittle-endian-data:--little-endian-data} %(asm_cpu)"
Index: config/sparc/sparc-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc-protos.h,v
retrieving revision 1.17.8.4
diff -c -p -d -r1.17.8.4 sparc-protos.h
*** config/sparc/sparc-protos.h 2002/03/30 20:59:18 1.17.8.4
--- config/sparc/sparc-protos.h 2002/03/31 03:01:32
*************** Boston, MA 02111-1307, USA. */
*** 24,29 ****
--- 24,31 ----
#ifndef __SPARC_PROTOS_H__
#define __SPARC_PROTOS_H__
+ extern bool sparc_emitting_epilogue;
+
#ifdef TREE_CODE
extern struct rtx_def *function_value PARAMS ((tree, enum machine_mode, int));
extern void function_arg_advance PARAMS ((CUMULATIVE_ARGS *,
*************** extern void sparc_emit_set_symbolic_cons
*** 84,90 ****
extern int sparc_splitdi_legitimate PARAMS ((rtx, rtx));
extern int sparc_absnegfloat_split_legitimate PARAMS ((rtx, rtx));
extern char *output_cbranch PARAMS ((rtx, rtx, int, int, int, int, rtx));
- extern const char *output_return PARAMS ((rtx *));
extern const char *output_sibcall PARAMS ((rtx, rtx));
extern char *output_v9branch PARAMS ((rtx, rtx, int, int, int, int, int,
rtx));
--- 86,91 ----
*************** extern char *sparc_v8plus_shift PARAMS (
*** 115,121 ****
/* Function used for V8+ code generation. Returns 1 if the high
32 bits of REG are 0 before INSN. */
extern int sparc_check_64 PARAMS ((rtx, rtx));
- extern int sparc_return_peephole_ok PARAMS ((rtx, rtx));
extern rtx gen_df_reg PARAMS ((rtx, int));
#endif /* RTX_CODE */
--- 116,121 ----
Index: config/sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.c,v
retrieving revision 1.185.2.9
diff -c -p -d -r1.185.2.9 sparc.c
*** config/sparc/sparc.c 2002/03/30 20:59:18 1.185.2.9
--- config/sparc/sparc.c 2002/03/31 03:01:33
*************** Boston, MA 02111-1307, USA. */
*** 68,85 ****
static int apparent_fsize;
static int actual_fsize;
! /* Number of live general or floating point registers needed to be saved
! (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
static int num_gfregs;
/* Save the operands last given to a compare for use when we
generate a scc or bcc insn. */
-
rtx sparc_compare_op0, sparc_compare_op1;
! /* We may need an epilogue if we spill too many registers.
! If this is non-zero, then we branch here for the epilogue. */
! static rtx leaf_label;
#ifdef LEAF_REGISTERS
--- 68,84 ----
static int apparent_fsize;
static int actual_fsize;
! /* Number of live general or floating point registers needed to be
! saved (as 4-byte quantities). */
static int num_gfregs;
/* Save the operands last given to a compare for use when we
generate a scc or bcc insn. */
rtx sparc_compare_op0, sparc_compare_op1;
! /* Coordinate with the md file wrt special insns created by
! sparc_nonflat_function_epilogue. */
! bool sparc_emitting_epilogue;
#ifdef LEAF_REGISTERS
*************** compute_frame_size (size, leaf_function)
*** 3392,3422 ****
int outgoing_args_size = (current_function_outgoing_args_size
+ REG_PARM_STACK_SPACE (current_function_decl));
! if (TARGET_EPILOGUE)
! {
! /* N_REGS is the number of 4-byte regs saved thus far. This applies
! even to v9 int regs to be consistent with save_regs/restore_regs. */
!
! if (TARGET_ARCH64)
! {
! for (i = 0; i < 8; i++)
! if (regs_ever_live[i] && ! call_used_regs[i])
! n_regs += 2;
! }
! else
! {
! for (i = 0; i < 8; i += 2)
! if ((regs_ever_live[i] && ! call_used_regs[i])
! || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
! n_regs += 2;
! }
! for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
if ((regs_ever_live[i] && ! call_used_regs[i])
|| (regs_ever_live[i+1] && ! call_used_regs[i+1]))
n_regs += 2;
}
/* Set up values for use in `function_epilogue'. */
num_gfregs = n_regs;
--- 3391,3418 ----
int outgoing_args_size = (current_function_outgoing_args_size
+ REG_PARM_STACK_SPACE (current_function_decl));
! /* N_REGS is the number of 4-byte regs saved thus far. This applies
! even to v9 int regs to be consistent with save_regs/restore_regs. */
! if (TARGET_ARCH64)
! {
! for (i = 0; i < 8; i++)
! if (regs_ever_live[i] && ! call_used_regs[i])
! n_regs += 2;
! }
! else
! {
! for (i = 0; i < 8; i += 2)
if ((regs_ever_live[i] && ! call_used_regs[i])
|| (regs_ever_live[i+1] && ! call_used_regs[i+1]))
n_regs += 2;
}
+ for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
+ if ((regs_ever_live[i] && ! call_used_regs[i])
+ || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
+ n_regs += 2;
+
/* Set up values for use in `function_epilogue'. */
num_gfregs = n_regs;
*************** sparc_nonflat_function_prologue (file, s
*** 3640,3663 ****
base = frame_base_name;
}
! n_regs = 0;
! if (TARGET_EPILOGUE && ! leaf_function)
! /* ??? Originally saved regs 0-15 here. */
! n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
! else if (leaf_function)
! /* ??? Originally saved regs 0-31 here. */
! n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
! if (TARGET_EPILOGUE)
! save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
! real_offset);
! }
!
! leaf_label = 0;
! if (leaf_function && actual_fsize != 0)
! {
! /* warning ("leaf procedure with frame size %d", actual_fsize); */
! if (! TARGET_EPILOGUE)
! leaf_label = gen_label_rtx ();
}
}
--- 3636,3644 ----
base = frame_base_name;
}
! n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
! save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
! real_offset);
}
}
*************** output_restore_regs (file, leaf_function
*** 3684,3698 ****
base = frame_base_name;
}
! n_regs = 0;
! if (TARGET_EPILOGUE && ! leaf_function)
! /* ??? Originally saved regs 0-15 here. */
! n_regs = restore_regs (file, 0, 8, base, offset, 0);
! else if (leaf_function)
! /* ??? Originally saved regs 0-31 here. */
! n_regs = restore_regs (file, 0, 8, base, offset, 0);
! if (TARGET_EPILOGUE)
! restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
}
/* This function generates the assembly code for function exit,
--- 3665,3672 ----
base = frame_base_name;
}
! n_regs = restore_regs (file, 0, 8, base, offset, 0);
! restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
}
/* This function generates the assembly code for function exit,
*************** sparc_nonflat_function_epilogue (file, s
*** 3725,3736 ****
{
const char *ret;
- if (leaf_label)
- {
- emit_label_after (leaf_label, get_last_insn ());
- final_scan_insn (get_last_insn (), file, 0, 0, 1);
- }
-
if (current_function_epilogue_delay_list == 0)
{
/* If code does not drop into the epilogue, we need
--- 3699,3704 ----
*************** sparc_nonflat_function_epilogue (file, s
*** 3751,3845 ****
else
ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
! if (TARGET_EPILOGUE || leaf_label)
{
! int old_target_epilogue = TARGET_EPILOGUE;
! target_flags &= ~old_target_epilogue;
! if (! leaf_function)
{
! if (current_function_calls_eh_return)
! {
! if (current_function_epilogue_delay_list)
! abort ();
! if (SKIP_CALLERS_UNIMP_P)
! abort ();
! fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
}
! /* If we wound up with things in our delay slot, flush them here. */
! else if (current_function_epilogue_delay_list)
{
! rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
! if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
! {
! epilogue_renumber (&delay, 0);
! fputs (SKIP_CALLERS_UNIMP_P
! ? "\treturn\t%i7+12\n"
! : "\treturn\t%i7+8\n", file);
! final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0);
! }
! else
! {
! rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
! get_last_insn ());
! rtx src;
! if (GET_CODE (delay) != SET)
abort();
! src = SET_SRC (delay);
! if (GET_CODE (src) == ASHIFT)
! {
! if (XEXP (src, 1) != const1_rtx)
! abort();
! SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
! XEXP (src, 0));
! }
! PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
! gen_rtvec (2, delay, PATTERN (insn)));
! final_scan_insn (insn, file, 1, 0, 1);
! }
}
- else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
- fputs ("\treturn\t%i7+8\n\tnop\n", file);
- else
- fprintf (file, "\t%s\n\trestore\n", ret);
}
! else if (current_function_calls_eh_return)
abort ();
! /* All of the following cases are for leaf functions. */
! else if (current_function_epilogue_delay_list)
! {
! /* eligible_for_epilogue_delay_slot ensures that if this is a
! leaf function, then we will only have insn in the delay slot
! if the frame size is zero, thus no adjust for the stack is
! needed here. */
! if (actual_fsize != 0)
! abort ();
! fprintf (file, "\t%s\n", ret);
! final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
! file, 1, 0, 1);
! }
! /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
! avoid generating confusing assembly language output. */
! else if (actual_fsize == 0)
! fprintf (file, "\t%s\n\tnop\n", ret);
! else if (actual_fsize <= 4096)
! fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
! else if (actual_fsize <= 8192)
! fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
! ret, actual_fsize - 4096);
! else if ((actual_fsize & 0x3ff) == 0)
! fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
! actual_fsize, ret);
! else
! fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
! actual_fsize, actual_fsize, ret);
! target_flags |= old_target_epilogue;
}
output_vectors:
sparc_output_deferred_case_vectors ();
--- 3719,3811 ----
else
ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
! if (! leaf_function)
{
! if (current_function_calls_eh_return)
! {
! if (current_function_epilogue_delay_list)
! abort ();
! if (SKIP_CALLERS_UNIMP_P)
! abort ();
! fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
! }
! /* If we wound up with things in our delay slot, flush them here. */
! else if (current_function_epilogue_delay_list)
{
! rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
! if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
! {
! epilogue_renumber (&delay, 0);
! fputs (SKIP_CALLERS_UNIMP_P
! ? "\treturn\t%i7+12\n"
! : "\treturn\t%i7+8\n", file);
! final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
! file, 1, 0, 0);
}
! else
{
! rtx insn, src;
! if (GET_CODE (delay) != SET)
! abort();
! src = SET_SRC (delay);
! if (GET_CODE (src) == ASHIFT)
! {
! if (XEXP (src, 1) != const1_rtx)
abort();
+ SET_SRC (delay)
+ = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
+ XEXP (src, 0));
+ }
! insn = gen_rtx_PARALLEL (VOIDmode,
! gen_rtvec (2, delay,
! gen_rtx_RETURN (VOIDmode)));
! insn = emit_jump_insn (insn);
! sparc_emitting_epilogue = true;
! final_scan_insn (insn, file, 1, 0, 1);
! sparc_emitting_epilogue = false;
}
}
! else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
! fputs ("\treturn\t%i7+8\n\tnop\n", file);
! else
! fprintf (file, "\t%s\n\trestore\n", ret);
! }
! /* All of the following cases are for leaf functions. */
! else if (current_function_calls_eh_return)
! abort ();
! else if (current_function_epilogue_delay_list)
! {
! /* eligible_for_epilogue_delay_slot ensures that if this is a
! leaf function, then we will only have insn in the delay slot
! if the frame size is zero, thus no adjust for the stack is
! needed here. */
! if (actual_fsize != 0)
abort ();
! fprintf (file, "\t%s\n", ret);
! final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
! file, 1, 0, 1);
}
+ /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
+ avoid generating confusing assembly language output. */
+ else if (actual_fsize == 0)
+ fprintf (file, "\t%s\n\tnop\n", ret);
+ else if (actual_fsize <= 4096)
+ fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
+ else if (actual_fsize <= 8192)
+ fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
+ ret, actual_fsize - 4096);
+ else if ((actual_fsize & 0x3ff) == 0)
+ fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
+ actual_fsize, ret);
+ else
+ fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
+ actual_fsize, actual_fsize, ret);
output_vectors:
sparc_output_deferred_case_vectors ();
*************** epilogue_renumber (where, test)
*** 5699,5785 ****
}
return 0;
}
-
- /* Output assembler code to return from a function. */
-
- const char *
- output_return (operands)
- rtx *operands;
- {
- rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
-
- if (leaf_label)
- {
- operands[0] = leaf_label;
- return "b%* %l0%(";
- }
- else if (current_function_uses_only_leaf_regs)
- {
- /* No delay slot in a leaf function. */
- if (delay)
- abort ();
-
- /* If we didn't allocate a frame pointer for the current function,
- the stack pointer might have been adjusted. Output code to
- restore it now. */
-
- operands[0] = GEN_INT (actual_fsize);
-
- /* Use sub of negated value in first two cases instead of add to
- allow actual_fsize == 4096. */
-
- if (actual_fsize <= 4096)
- {
- if (SKIP_CALLERS_UNIMP_P)
- return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
- else
- return "retl\n\tsub\t%%sp, -%0, %%sp";
- }
- else if (actual_fsize <= 8192)
- {
- operands[0] = GEN_INT (actual_fsize - 4096);
- if (SKIP_CALLERS_UNIMP_P)
- return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
- else
- return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
- }
- else if (SKIP_CALLERS_UNIMP_P)
- {
- if ((actual_fsize & 0x3ff) != 0)
- return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
- else
- return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
- }
- else
- {
- if ((actual_fsize & 0x3ff) != 0)
- return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
- else
- return "sethi\t%%hi(%a0), %%g1\n\tretl\n\tadd\t%%sp, %%g1, %%sp";
- }
- }
- else if (TARGET_V9)
- {
- if (delay)
- {
- epilogue_renumber (&SET_DEST (PATTERN (delay)), 0);
- epilogue_renumber (&SET_SRC (PATTERN (delay)), 0);
- }
- if (SKIP_CALLERS_UNIMP_P)
- return "return\t%%i7+12%#";
- else
- return "return\t%%i7+8%#";
- }
- else
- {
- if (delay)
- abort ();
- if (SKIP_CALLERS_UNIMP_P)
- return "jmp\t%%i7+12\n\trestore";
- else
- return "ret\n\trestore";
- }
- }
/* Leaf functions and non-leaf functions have different needs. */
--- 5665,5670 ----
*************** sparc_v8plus_shift (operands, insn, opco
*** 8597,8619 ****
else
return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
}
-
-
- /* Return 1 if DEST and SRC reference only global and in registers. */
-
- int
- sparc_return_peephole_ok (dest, src)
- rtx dest, src;
- {
- if (! TARGET_V9)
- return 0;
- if (current_function_uses_only_leaf_regs)
- return 0;
- if (GET_CODE (src) != CONST_INT
- && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
- return 0;
- return IN_OR_GLOBAL_P (dest);
- }
/* Output rtl to increment the profiler label LABELNO
for profiling a function entry. */
--- 8482,8487 ----
*************** sparc_add_gc_roots ()
*** 8655,8661 ****
{
ggc_add_rtx_root (&sparc_compare_op0, 1);
ggc_add_rtx_root (&sparc_compare_op1, 1);
- ggc_add_rtx_root (&leaf_label, 1);
ggc_add_rtx_root (&global_offset_table, 1);
ggc_add_rtx_root (&get_pc_symbol, 1);
ggc_add_rtx_root (&sparc_addr_diff_list, 1);
--- 8523,8528 ----
Index: config/sparc/sparc.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.h,v
retrieving revision 1.161.2.8
diff -c -p -d -r1.161.2.8 sparc.h
*** config/sparc/sparc.h 2002/03/30 20:59:19 1.161.2.8
--- config/sparc/sparc.h 2002/03/31 03:01:33
*************** extern int target_flags;
*** 387,397 ****
#define MASK_FPU 1
#define TARGET_FPU (target_flags & MASK_FPU)
- /* Nonzero if we should use function_epilogue(). Otherwise, we
- use fast return insns, but lose some generality. */
- #define MASK_EPILOGUE 2
- #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
-
/* Nonzero if we should assume that double pointers might be unaligned.
This can happen when linking gcc compiled code with other compilers,
because the ABI only guarantees 4 byte alignment. */
--- 387,392 ----
*************** extern int target_flags;
*** 535,544 ****
{"soft-float", -MASK_FPU, \
N_("Do not use hardware fp") }, \
{"soft-float", MASK_FPU_SET, NULL }, \
- {"epilogue", MASK_EPILOGUE, \
- N_("Use function_epilogue()") }, \
- {"no-epilogue", -MASK_EPILOGUE, \
- N_("Do not use function_epilogue()") }, \
{"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \
N_("Assume possible double misalignment") }, \
{"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \
--- 530,535 ----
*************** extern int target_flags;
*** 607,613 ****
/* MASK_APP_REGS must always be the default because that's what
FIXED_REGISTERS is set to and -ffixed- is processed before
CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
/* This is meant to be redefined in target specific files. */
#define SUBTARGET_SWITCHES
--- 598,604 ----
/* MASK_APP_REGS must always be the default because that's what
FIXED_REGISTERS is set to and -ffixed- is processed before
CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
/* This is meant to be redefined in target specific files. */
#define SUBTARGET_SWITCHES
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.148.2.3
diff -c -p -d -r1.148.2.3 sparc.md
*** config/sparc/sparc.md 2002/03/29 08:22:23 1.148.2.3
--- config/sparc/sparc.md 2002/03/31 03:01:33
***************
*** 8744,8764 ****
[(set_attr "type" "multi")
(set_attr "length" "3")])
- (define_insn "return"
- [(return)
- (use (reg:SI 31))]
- "! TARGET_EPILOGUE"
- "* return output_return (operands);"
- [(set_attr "type" "return")])
-
- (define_peephole
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "arith_operand" "rI"))
- (parallel [(return)
- (use (reg:SI 31))])]
- "sparc_return_peephole_ok (operands[0], operands[1])"
- "return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0")
-
(define_insn "nop"
[(const_int 0)]
""
--- 8744,8749 ----
***************
*** 9155,9168 ****
(compare:CC (match_dup 1) (const_int 0)))])]
"")
! ;; Return peepholes. First the "normal" ones.
! ;; These are necessary to catch insns ending up in the epilogue delay list.
(define_insn "*return_qi"
[(set (match_operand:QI 0 "restore_operand" "")
(match_operand:QI 1 "arith_operand" "rI"))
(return)]
! "! TARGET_EPILOGUE"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
--- 9140,9153 ----
(compare:CC (match_dup 1) (const_int 0)))])]
"")
! ;; Return peepholes. These are generated by sparc_nonflat_function_epilogue
! ;; who then immediately calls final_scan_insn.
(define_insn "*return_qi"
[(set (match_operand:QI 0 "restore_operand" "")
(match_operand:QI 1 "arith_operand" "rI"))
(return)]
! "sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
***************
*** 9180,9186 ****
[(set (match_operand:HI 0 "restore_operand" "")
(match_operand:HI 1 "arith_operand" "rI"))
(return)]
! "! TARGET_EPILOGUE"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
--- 9165,9171 ----
[(set (match_operand:HI 0 "restore_operand" "")
(match_operand:HI 1 "arith_operand" "rI"))
(return)]
! "sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
***************
*** 9198,9204 ****
[(set (match_operand:SI 0 "restore_operand" "")
(match_operand:SI 1 "arith_operand" "rI"))
(return)]
! "! TARGET_EPILOGUE"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
--- 9183,9189 ----
[(set (match_operand:SI 0 "restore_operand" "")
(match_operand:SI 1 "arith_operand" "rI"))
(return)]
! "sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
***************
*** 9212,9226 ****
[(set_attr "type" "multi")
(set_attr "length" "2")])
- ;; The following pattern is only generated by delayed-branch scheduling,
- ;; when the insn winds up in the epilogue. This can happen not only when
- ;; ! TARGET_FPU because we move complex types around by parts using
- ;; SF mode SUBREGs.
(define_insn "*return_sf_no_fpu"
[(set (match_operand:SF 0 "restore_operand" "=r")
(match_operand:SF 1 "register_operand" "r"))
(return)]
! "! TARGET_EPILOGUE"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
--- 9197,9207 ----
[(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_sf_no_fpu"
[(set (match_operand:SF 0 "restore_operand" "=r")
(match_operand:SF 1 "register_operand" "r"))
(return)]
! "sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
***************
*** 9237,9243 ****
[(set (match_operand:DF 0 "restore_operand" "=r")
(match_operand:DF 1 "register_operand" "r"))
(return)]
! "! TARGET_EPILOGUE && TARGET_ARCH64"
"*
{
if (IN_OR_GLOBAL_P (operands[1]))
--- 9218,9224 ----
[(set (match_operand:DF 0 "restore_operand" "=r")
(match_operand:DF 1 "register_operand" "r"))
(return)]
! "sparc_emitting_epilogue && TARGET_ARCH64"
"*
{
if (IN_OR_GLOBAL_P (operands[1]))
***************
*** 9253,9259 ****
(plus:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))
(return)]
! "! TARGET_EPILOGUE"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
--- 9234,9240 ----
(plus:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))
(return)]
! "sparc_emitting_epilogue"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
***************
*** 9274,9280 ****
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "in")))
(return)]
! "! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
--- 9255,9261 ----
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "in")))
(return)]
! "sparc_emitting_epilogue && ! TARGET_CM_MEDMID"
"*
{
if (! TARGET_ARCH64 && current_function_returns_struct)
***************
*** 9292,9298 ****
[(set (match_operand:DI 0 "restore_operand" "")
(match_operand:DI 1 "arith_double_operand" "rHI"))
(return)]
! "TARGET_ARCH64 && ! TARGET_EPILOGUE"
"ret\;restore %%g0, %1, %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
--- 9273,9279 ----
[(set (match_operand:DI 0 "restore_operand" "")
(match_operand:DI 1 "arith_double_operand" "rHI"))
(return)]
! "sparc_emitting_epilogue && TARGET_ARCH64"
"ret\;restore %%g0, %1, %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
***************
*** 9302,9308 ****
(plus:DI (match_operand:DI 1 "arith_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
(return)]
! "TARGET_ARCH64 && ! TARGET_EPILOGUE"
"ret\;restore %r1, %2, %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
--- 9283,9289 ----
(plus:DI (match_operand:DI 1 "arith_operand" "%r")
(match_operand:DI 2 "arith_double_operand" "rHI")))
(return)]
! "sparc_emitting_epilogue && TARGET_ARCH64"
"ret\;restore %r1, %2, %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
***************
*** 9312,9329 ****
(lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
(match_operand:DI 2 "immediate_operand" "in")))
(return)]
! "TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
"ret\;restore %r1, %%lo(%a2), %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
- ;; The following pattern is only generated by delayed-branch scheduling,
- ;; when the insn winds up in the epilogue.
(define_insn "*return_sf"
[(set (reg:SF 32)
(match_operand:SF 0 "register_operand" "f"))
(return)]
! "! TARGET_EPILOGUE"
"ret\;fmovs\\t%0, %%f0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
--- 9293,9308 ----
(lo_sum:DI (match_operand:DI 1 "arith_operand" "%r")
(match_operand:DI 2 "immediate_operand" "in")))
(return)]
! "sparc_emitting_epilogue && TARGET_ARCH64 && ! TARGET_CM_MEDMID"
"ret\;restore %r1, %%lo(%a2), %Y0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
(define_insn "*return_sf"
[(set (reg:SF 32)
(match_operand:SF 0 "register_operand" "f"))
(return)]
! "sparc_emitting_epilogue"
"ret\;fmovs\\t%0, %%f0"
[(set_attr "type" "multi")
(set_attr "length" "2")])
Index: config/sparc/splet.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/splet.h,v
retrieving revision 1.10
diff -c -p -d -r1.10 splet.h
*** config/sparc/splet.h 2001/11/14 21:44:21 1.10
--- config/sparc/splet.h 2002/03/31 03:01:33
*************** the Free Software Foundation, 59 Temple
*** 20,26 ****
Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
#define CPP_PREDEFINES "-Dsparc -Acpu=sparc -Amachine=sparc"
--- 20,26 ----
Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT MASK_APP_REGS
#define CPP_PREDEFINES "-Dsparc -Acpu=sparc -Amachine=sparc"
Index: config/sparc/vxsparc64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/vxsparc64.h,v
retrieving revision 1.3
diff -c -p -d -r1.3 vxsparc64.h
*** config/sparc/vxsparc64.h 2001/11/12 23:52:28 1.3
--- config/sparc/vxsparc64.h 2002/03/31 03:01:33
*************** Boston, MA 02111-1307, USA. */
*** 71,77 ****
#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) -DCPU=ULTRASPARC -D__CPU__=CPU"
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS | MASK_EPILOGUE | MASK_FPU \
| MASK_LONG_DOUBLE_128 | MASK_64BIT)
#undef SPARC_DEFAULT_CMODEL
--- 71,77 ----
#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) -DCPU=ULTRASPARC -D__CPU__=CPU"
#undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_APP_REGS | MASK_FPU \
| MASK_LONG_DOUBLE_128 | MASK_64BIT)
#undef SPARC_DEFAULT_CMODEL