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varargs for vectors
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org, dje at watson dot ibm dot com
- Date: Sat, 9 Mar 2002 09:21:08 +1100
- Subject: varargs for vectors
looks big, but it's rather a simple obvious fix.
for sysv4, vector varargs go in the overflow area. i just
conditionalized the code that looks in the register save area on
the type not being a vector.
and i made sure things got aligned properly when getting vectors
out of the overflow area.
obvious fix, but i'll wait on your ok anyhow.
cheers
2002-03-08 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.c (rs6000_va_arg): Fix alignment for
vectors.
Index: rs6000.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.257.4.6
diff -c -r1.257.4.6 rs6000.c
*** rs6000.c 2002/03/07 06:53:53 1.257.4.6
--- rs6000.c 2002/03/08 22:16:02
***************
*** 3178,3227 ****
lab_over = gen_label_rtx ();
addr_rtx = gen_reg_rtx (Pmode);
! emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
! GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
! lab_false);
!
! /* Long long is aligned in the registers. */
! if (n_reg > 1)
{
! u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
! build_int_2 (n_reg - 1, 0));
! u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
! u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
! TREE_SIDE_EFFECTS (u) = 1;
! expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
! }
! if (sav_ofs)
! t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
! else
! t = sav;
! u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0));
! TREE_SIDE_EFFECTS (u) = 1;
! u = build1 (CONVERT_EXPR, integer_type_node, u);
! TREE_SIDE_EFFECTS (u) = 1;
! u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
! TREE_SIDE_EFFECTS (u) = 1;
! t = build (PLUS_EXPR, ptr_type_node, t, u);
! TREE_SIDE_EFFECTS (t) = 1;
! r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
! if (r != addr_rtx)
! emit_move_insn (addr_rtx, r);
- emit_jump_insn (gen_jump (lab_over));
- emit_barrier ();
emit_label (lab_false);
/* ... otherwise out of the overflow area. */
! /* Make sure we don't find reg 7 for the next int arg. */
! if (n_reg > 1)
{
t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
TREE_SIDE_EFFECTS (t) = 1;
--- 3178,3239 ----
lab_over = gen_label_rtx ();
addr_rtx = gen_reg_rtx (Pmode);
! /* Vectors never go in registers. */
! if (TREE_CODE (type) != VECTOR_TYPE)
{
! TREE_THIS_VOLATILE (reg) = 1;
! emit_cmp_and_jump_insns
! (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
! GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
! lab_false);
!
! /* Long long is aligned in the registers. */
! if (n_reg > 1)
! {
! u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
! build_int_2 (n_reg - 1, 0));
! u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
! u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
! TREE_SIDE_EFFECTS (u) = 1;
! expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
! }
!
! if (sav_ofs)
! t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
! else
! t = sav;
! u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
! build_int_2 (n_reg, 0));
! TREE_SIDE_EFFECTS (u) = 1;
! u = build1 (CONVERT_EXPR, integer_type_node, u);
! TREE_SIDE_EFFECTS (u) = 1;
! u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
! TREE_SIDE_EFFECTS (u) = 1;
! t = build (PLUS_EXPR, ptr_type_node, t, u);
! TREE_SIDE_EFFECTS (t) = 1;
! r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
! if (r != addr_rtx)
! emit_move_insn (addr_rtx, r);
! emit_jump_insn (gen_jump (lab_over));
! emit_barrier ();
! }
emit_label (lab_false);
/* ... otherwise out of the overflow area. */
! /* Make sure we don't find reg 7 for the next int arg.
!
! All AltiVec vectors go in the overflow area. So in the AltiVec
! case we need to get the vectors from the overflow area, but
! remember where the GPRs and FPRs are. */
! if (n_reg > 1 && TREE_CODE (type) != VECTOR_TYPE)
{
t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
TREE_SIDE_EFFECTS (t) = 1;
***************
*** 3233,3240 ****
t = ovf;
else
{
! t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0));
! t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1));
}
t = save_expr (t);
--- 3245,3260 ----
t = ovf;
else
{
! int align;
!
! /* Vectors are 16 byte aligned. */
! if (TREE_CODE (type) == VECTOR_TYPE)
! align = 15;
! else
! align = 7;
!
! t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
! t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
}
t = save_expr (t);