This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: Combine known_cond() may create subreg of const_int
- From: Alexandre Oliva <aoliva at redhat dot com>
- To: andreas tobler <toa at pop dot agri dot ch>
- Cc: Richard Henderson <rth at redhat dot com>, gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: 21 Feb 2002 19:21:31 -0300
- Subject: Re: Combine known_cond() may create subreg of const_int
- Organization: GCC Team, Red Hat
- References: <or7kp67i4s.fsf@free.redhat.lsd.ic.unicamp.br><20020221221016.28476@pop.agri.ch>
On Feb 21, 2002, andreas tobler <toa@pop.agri.ch> wrote:
>> That's because the sparc port is buggy, and that's why I posted a
>> separate patch for it.
> Which one ? And why is sparc != sparc ? You mentioned the bootstrap sol2.7!?.
There were two patches in my posting, and RTH approved one of them.
> Great, I don't have time to as mentioned above. But I welcome test
> suggestions and I can run them in parallel to my job.
> Another thing which bothers me, as read on the dev plan I expect being on
> the final line for 3.1, why are breaks in now?
It's not a new bug. It's just a bug that was exposed by a new sanity
check. It would silently bite before.
> Mentioned above, I can test and I'll do so.
Here's the patch for sparc, again:
Index: gcc/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
* config/sparc/sol2.h: Don't include sys/mman.h.
* config/sparc/sparc.c (arith_operand): Use SMALL_INT32.
(arith_4096_operand): Don't throw high bits away.
(const64_operand): Take sign extension of CONST_INTs into account.
(const64_high_operand, sparc_emit_set_const32): Likewise.
(GEN_HIGHINT64): Likewise.
(sparc_emit_set_const64_quick1): Likewise.
(const64_is_2insns): Likewise.
(print_operand): Use trunc_int_for_mode for sign extension.
* config/sparc/sparc.h (SMALL_INT32): Likewise.
(SPARC_SETHI_P): Simplify.
* config/sparc/sparc.md (movqi): Sign-extend CONST_DOUBLE
chars. Assume CONST_INT is already properly sign-extended.
(movdi split): Sign-extend each SImode part.
(andsi3 split): Don't mask high bits off, so that result
remains properly sign-extend.
(iorsi3 split): Likewise.
(xorsi3 split): Likewise.
Index: gcc/config/sparc/sol2.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sol2.h,v
retrieving revision 1.35
diff -u -p -r1.35 sol2.h
--- gcc/config/sparc/sol2.h 2002/02/04 18:16:06 1.35
+++ gcc/config/sparc/sol2.h 2002/02/20 17:47:10
@@ -243,7 +243,7 @@ Boston, MA 02111-1307, USA. */
/* This declares mprotect (used in TRANSFER_FROM_TRAMPOLINE) for
libgcc2.c. */
-#ifdef L_trampoline
+#if 0 /* def L_trampoline */
#include <sys/mman.h>
#endif
Index: gcc/config/sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.c,v
retrieving revision 1.182
diff -u -p -r1.182 sparc.c
--- gcc/config/sparc/sparc.c 2002/02/07 18:48:13 1.182
+++ gcc/config/sparc/sparc.c 2002/02/20 17:47:15
@@ -950,13 +950,11 @@ arith_operand (op, mode)
rtx op;
enum machine_mode mode;
{
- int val;
if (register_operand (op, mode))
return 1;
if (GET_CODE (op) != CONST_INT)
return 0;
- val = INTVAL (op) & 0xffffffff;
- return SPARC_SIMM13_P (val);
+ return SMALL_INT32 (op);
}
/* Return true if OP is a constant 4096 */
@@ -969,7 +967,6 @@ arith_4096_operand (op, mode)
int val;
if (GET_CODE (op) != CONST_INT)
return 0;
- val = INTVAL (op) & 0xffffffff;
return val == 4096;
}
@@ -998,7 +995,7 @@ const64_operand (op, mode)
&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
&& (CONST_DOUBLE_HIGH (op) ==
((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
- (HOST_WIDE_INT)0xffffffff : 0)))
+ (HOST_WIDE_INT)-1 : 0)))
#endif
);
}
@@ -1010,7 +1007,7 @@ const64_high_operand (op, mode)
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return ((GET_CODE (op) == CONST_INT
- && (INTVAL (op) & 0xfffffc00) != 0
+ && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
&& SPARC_SETHI_P (INTVAL (op))
#if HOST_BITS_PER_WIDE_INT != 64
/* Must be positive on non-64bit host else the
@@ -1021,7 +1018,7 @@ const64_high_operand (op, mode)
)
|| (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op) == 0
- && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
+ && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
}
@@ -1335,11 +1332,13 @@ sparc_emit_set_const32 (op0, op1)
&& (INTVAL (op1) & 0x80000000) != 0)
emit_insn (gen_rtx_SET
(VOIDmode, temp,
- gen_rtx_CONST_DOUBLE (VOIDmode, INTVAL (op1) & 0xfffffc00,
+ gen_rtx_CONST_DOUBLE (VOIDmode,
+ INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
0)));
else
emit_insn (gen_rtx_SET (VOIDmode, temp,
- GEN_INT (INTVAL (op1) & 0xfffffc00)));
+ GEN_INT (INTVAL (op1)
+ & ~(HOST_WIDE_INT)0x3ff)));
emit_insn (gen_rtx_SET (VOIDmode,
op0,
@@ -1509,15 +1508,15 @@ static rtx gen_safe_OR64 PARAMS ((rtx, H
static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
#if HOST_BITS_PER_WIDE_INT == 64
-#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
+#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
#define GEN_INT64(__x) GEN_INT (__x)
#else
#define GEN_HIGHINT64(__x) \
- gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xfffffc00, 0)
+ gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0)
#define GEN_INT64(__x) \
gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \
((__x) & 0x80000000 \
- ? 0xffffffff : 0))
+ ? -1 : 0))
#endif
/* The optimizer is not to assume anything about exactly
@@ -1602,7 +1601,8 @@ sparc_emit_set_const64_quick1 (op0, temp
{
emit_insn (gen_rtx_SET (VOIDmode, op0,
gen_safe_XOR64 (temp,
- (-0x400 | (low_bits & 0x3ff)))));
+ (-(HOST_WIDE_INT)0x400
+ | (low_bits & 0x3ff)))));
}
}
}
@@ -1835,7 +1835,7 @@ const64_is_2insns (high_bits, low_bits)
int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
if (high_bits == 0
- || high_bits == 0xffffffff)
+ || high_bits == -1)
return 1;
analyze_64bit_constant (high_bits, low_bits,
@@ -6000,9 +6000,7 @@ print_operand (file, x, code)
case 'b':
{
/* Print a sign-extended character. */
- int i = INTVAL (x) & 0xff;
- if (i & 0x80)
- i |= 0xffffff00;
+ int i = trunc_int_for_mode (INTVAL (x), QImode);
fprintf (file, "%d", i);
return;
}
Index: gcc/config/sparc/sparc.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.h,v
retrieving revision 1.159
diff -u -p -r1.159 sparc.h
--- gcc/config/sparc/sparc.h 2002/02/06 06:58:31 1.159
+++ gcc/config/sparc/sparc.h 2002/02/20 17:47:18
@@ -1402,10 +1402,9 @@ extern const char leaf_reg_remap[];
SMALL_INT is used throughout the port so we continue to use it. */
#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
-#define SPARC_SETHI_P(X) \
-(((unsigned HOST_WIDE_INT) (X) & \
- (TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
+#define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
+ (INTVAL (X), SImode)))
+#define SPARC_SETHI_P(X) (((unsigned HOST_WIDE_INT) (X) & 0x3ff) == 0)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
Index: gcc/config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.146
diff -u -p -r1.146 sparc.md
--- gcc/config/sparc/sparc.md 2002/02/20 01:21:06 1.146
+++ gcc/config/sparc/sparc.md 2002/02/20 17:47:21
@@ -2053,15 +2053,9 @@
a double if needed. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
- operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xff);
+ operands[1] = GEN_INT (trunc_int_for_mode
+ (CONST_DOUBLE_LOW (operands[1]), QImode));
}
- else if (GET_CODE (operands[1]) == CONST_INT)
- {
- /* And further, we know for all QI cases that only the
- low byte is significant, which we can always process
- in a single insn. So mask it now. */
- operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
- }
/* Handle sets of MEM first. */
if (GET_CODE (operands[0]) == MEM)
@@ -2769,8 +2763,8 @@
#else
unsigned int low, high;
- low = INTVAL (operands[1]) & 0xffffffff;
- high = (INTVAL (operands[1]) >> 32) & 0xffffffff;
+ low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
+ high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));
/* Slick... but this trick loses if this subreg constant part
@@ -6574,7 +6568,7 @@
(set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
;; Split DImode logical operations requiring two instructions.
@@ -6717,7 +6711,7 @@
(set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
(define_insn "*or_not_di_sp32"
@@ -6833,7 +6827,7 @@
(set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
(define_split
@@ -6848,7 +6842,7 @@
(set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{cygnus.com, redhat.com}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer