This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: powerpc patch 3 of 9
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: David Edelsohn <dje at watson dot ibm dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Fri, 22 Feb 2002 00:34:53 +1030
- Subject: Re: powerpc patch 3 of 9
- References: <20020220110046.GJ1054@bubble.sa.bigpond.net.au>
Here's a revised patch.
Enables use of a bunch of SImode insns on PowerPC64, and fixes bad
code generated on PowerPC64 targets for
unsigned long foo (unsigned long base, unsigned int val)
{
return base + (val & 0x80000001);
}
and a number of other cases involving rlwinm.
* config/rs6000/rs6000.c (mask_operand): Don't allow masks that
wrap on PowerPC64 targets.
(mask_operand_wrap): New predicate.
(extract_MB, extract_ME): New functions split out of..
(print_operand): ..here.
* config/rs6000/rs6000-protos.h (mask_operand_wrap): Declare.
(extract_MB, extract_ME): Likewise.
* config/rs6000/rs6000.h (PREDICATE_CODES): Add mask_operand_wrap.
* config/rs6000/rs6000.md: Enable many insns involving rlwinm for
TARGET_POWERPC64. Handle rlwinm corner cases. Remove redundant
`T' constraint from patterns using mask_operand.
The mask_operand patch could be applied without the other changes to
fix the bad code generation.
--
Alan Modra
IBM OzLabs - Linux Technology Centre
diff -urpN -xCVS -x*~ -xTAGS gcc-ppc64-31.orig/gcc/config/rs6000/rs6000-protos.h gcc-ppc64-31/gcc/config/rs6000/rs6000-protos.h
--- gcc-ppc64-31.orig/gcc/config/rs6000/rs6000-protos.h Thu Feb 21 10:49:53 2002
+++ gcc-ppc64-31/gcc/config/rs6000/rs6000-protos.h Thu Feb 21 23:48:51 2002
@@ -61,6 +61,7 @@ extern int non_add_cint_operand PARAMS (
extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode));
extern int logical_operand PARAMS ((rtx, enum machine_mode));
extern int mask_operand PARAMS ((rtx, enum machine_mode));
+extern int mask_operand_wrap PARAMS ((rtx, enum machine_mode));
extern int mask64_operand PARAMS ((rtx, enum machine_mode));
extern int and64_operand PARAMS ((rtx, enum machine_mode));
extern int and_operand PARAMS ((rtx, enum machine_mode));
@@ -95,6 +96,8 @@ extern int addrs_ok_for_quad_peep PARAMS
extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,
enum machine_mode, rtx));
extern int ccr_bit PARAMS ((rtx, int));
+extern int extract_MB PARAMS ((rtx));
+extern int extract_ME PARAMS ((rtx));
extern void print_operand PARAMS ((FILE *, rtx, int));
extern void print_operand_address PARAMS ((FILE *, rtx));
extern enum rtx_code rs6000_reverse_condition PARAMS ((enum machine_mode,
diff -urpN -xCVS -x*~ -xTAGS gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.c gcc-ppc64-31/gcc/config/rs6000/rs6000.c
--- gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.c Thu Feb 21 18:45:18 2002
+++ gcc-ppc64-31/gcc/config/rs6000/rs6000.c Thu Feb 21 23:56:07 2002
@@ -1399,6 +1401,17 @@ mask_operand (op, mode)
c = INTVAL (op);
+ /* We have to be careful here. This predicate is used when generating
+ rlwinm instructions. On PowerPC64, rlwinm copies the low 32 bits
+ of the reg to the high 32 bits, rotates, then masks. The mask is
+ generated from bits MB+32 thru ME+32, and if it wraps (ie. MB > ME)
+ will have 1's in the high order 32 bits. In cases where we are
+ using the instruction to set CR0 we would end up with the wrong
+ condition codes, and we confuse gcc in cases where it knows the
+ high bits are zero. */
+ if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
+ return 0;
+
/* We don't change the number of transitions by inverting,
so make sure we start with the LS bit zero. */
if (c & 1)
@@ -1424,6 +1437,18 @@ mask_operand (op, mode)
return c == -lsb;
}
+/* Return 1 for the PowerPC64 rlwinm corner case. */
+
+int
+mask_operand_wrap (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ return (GET_CODE (op) == CONST_INT
+ && INTVAL (op) != -1
+ && (INTVAL (op) & 0x80000001) == 0x80000001);
+}
+
/* Return 1 if the operand is a constant that is a PowerPC64 mask.
It is if there are no more than one 1->0 or 0->1 transitions.
Reject all ones and all zeros, since these should have been optimized
@@ -6145,6 +6169,79 @@ rs6000_free_machine_status (p)
}
+ /* These macros test for integers and extract the low-order bits. */
+#define INT_P(X) \
+((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
+ && GET_MODE (X) == VOIDmode)
+
+#define INT_LOWPART(X) \
+ (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
+
+int
+extract_MB (op)
+ rtx op;
+{
+ int i;
+ HOST_WIDE_INT val = INT_LOWPART (op);
+
+ /* If the high bit is set and the low bit is not, the value is zero.
+ If the high bit is zero, the value is the first 1 bit we find from
+ the left. */
+ if ((val & 0x80000000) && ((val & 1) == 0))
+ return 0;
+
+ if ((val & 0x80000000) == 0)
+ {
+ for (i = 1; i < 32; i++)
+ if ((val <<= 1) & 0x80000000)
+ break;
+ return i;
+ }
+
+ /* Otherwise, look for the first 0 bit from the right. The result is its
+ number plus 1. We know the low-order bit is one. */
+ for (i = 0; i < 32; i++)
+ if (((val >>= 1) & 1) == 0)
+ break;
+
+ /* If we ended in ...01, i would be 0. The correct value is 31, so
+ we want 31 - i. */
+ return 31 - i;
+}
+
+int
+extract_ME (op)
+ rtx op;
+{
+ int i;
+ HOST_WIDE_INT val = INT_LOWPART (op);
+
+ /* If the low bit is set and the high bit is not, the value is 31.
+ If the low bit is zero, the value is the first 1 bit we find from
+ the right. */
+ if ((val & 1) && ((val & 0x80000000) == 0))
+ return 31;
+
+ if ((val & 1) == 0)
+ {
+ for (i = 0; i < 32; i++)
+ if ((val >>= 1) & 1)
+ break;
+
+ /* If we had ....10, i would be 0. The result should be
+ 30, so we need 30 - i. */
+ return 30 - i;
+ }
+
+ /* Otherwise, look for the first 0 bit from the left. The result is its
+ number minus 1. We know the high-order bit is one. */
+ for (i = 0; i < 32; i++)
+ if (((val <<= 1) & 0x80000000) == 0)
+ break;
+
+ return i;
+}
+
/* Print an operand. Recognize special options, documented below. */
#if TARGET_ELF
@@ -6164,14 +6261,6 @@ print_operand (file, x, code)
int i;
HOST_WIDE_INT val;
- /* These macros test for integers and extract the low-order bits. */
-#define INT_P(X) \
-((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
- && GET_MODE (X) == VOIDmode)
-
-#define INT_LOWPART(X) \
- (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
-
switch (code)
{
case '.':
@@ -6381,34 +6470,7 @@ print_operand (file, x, code)
if (! mask_operand (x, SImode))
output_operand_lossage ("invalid %%m value");
- val = INT_LOWPART (x);
-
- /* If the high bit is set and the low bit is not, the value is zero.
- If the high bit is zero, the value is the first 1 bit we find from
- the left. */
- if ((val & 0x80000000) && ((val & 1) == 0))
- {
- putc ('0', file);
- return;
- }
- else if ((val & 0x80000000) == 0)
- {
- for (i = 1; i < 32; i++)
- if ((val <<= 1) & 0x80000000)
- break;
- fprintf (file, "%d", i);
- return;
- }
-
- /* Otherwise, look for the first 0 bit from the right. The result is its
- number plus 1. We know the low-order bit is one. */
- for (i = 0; i < 32; i++)
- if (((val >>= 1) & 1) == 0)
- break;
-
- /* If we ended in ...01, i would be 0. The correct value is 31, so
- we want 31 - i. */
- fprintf (file, "%d", 31 - i);
+ fprintf (file, "%d", extract_MB (x));
return;
case 'M':
@@ -6416,35 +6478,7 @@ print_operand (file, x, code)
if (! mask_operand (x, SImode))
output_operand_lossage ("invalid %%M value");
- val = INT_LOWPART (x);
-
- /* If the low bit is set and the high bit is not, the value is 31.
- If the low bit is zero, the value is the first 1 bit we find from
- the right. */
- if ((val & 1) && ((val & 0x80000000) == 0))
- {
- fputs ("31", file);
- return;
- }
- else if ((val & 1) == 0)
- {
- for (i = 0; i < 32; i++)
- if ((val >>= 1) & 1)
- break;
-
- /* If we had ....10, i would be 0. The result should be
- 30, so we need 30 - i. */
- fprintf (file, "%d", 30 - i);
- return;
- }
-
- /* Otherwise, look for the first 0 bit from the left. The result is its
- number minus 1. We know the high-order bit is one. */
- for (i = 0; i < 32; i++)
- if (((val <<= 1) & 0x80000000) == 0)
- break;
-
- fprintf (file, "%d", i);
+ fprintf (file, "%d", extract_ME (x));
return;
/* %n outputs the negative of its operand. */
diff -urpN -xCVS -x*~ -xTAGS gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.h gcc-ppc64-31/gcc/config/rs6000/rs6000.h
--- gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.h Thu Feb 21 18:45:18 2002
+++ gcc-ppc64-31/gcc/config/rs6000/rs6000.h Thu Feb 21 23:49:01 2002
@@ -2745,6 +2745,7 @@ extern char rs6000_reg_names[][8]; /* re
{"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
{"mask_operand", {CONST_INT}}, \
+ {"mask_operand_wrap", {CONST_INT}}, \
{"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
{"count_register_operand", {REG}}, \
{"xer_operand", {REG}}, \
diff -urpN -xCVS -x*~ -xTAGS gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.md gcc-ppc64-31/gcc/config/rs6000/rs6000.md
--- gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.md Thu Feb 21 10:50:04 2002
+++ gcc-ppc64-31/gcc/config/rs6000/rs6000.md Thu Feb 21 23:49:01 2002
@@ -2814,7 +2815,7 @@
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "! TARGET_POWERPC64"
+ ""
"@
and. %3,%1,%2
{andil.|andi.} %3,%1,%b2
@@ -2834,7 +2835,7 @@
(const_int 0)))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:CC 4 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(parallel [(set (match_dup 3)
(and:SI (match_dup 1)
(match_dup 2)))
@@ -2853,7 +2854,7 @@
(and:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
- "! TARGET_POWERPC64"
+ ""
"@
and. %0,%1,%2
{andil.|andi.} %0,%1,%b2
@@ -2875,7 +2876,7 @@
(and:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:CC 4 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(parallel [(set (match_dup 0)
(and:SI (match_dup 1)
(match_dup 2)))
@@ -2885,6 +2886,84 @@
(const_int 0)))]
"")
+;; Handle the PowerPC64 rlwinm corner case
+(define_insn_and_split "*andsi3_internal4"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "mask_operand_wrap" "")))]
+ "TARGET_POWERPC64"
+ "#"
+ "TARGET_POWERPC64"
+ [(set (match_dup 0)
+ (and:SI (rotate:SI (match_dup 1) (match_dup 3))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (rotate:SI (match_dup 0) (match_dup 5)))]
+ "
+{
+ int mb = extract_MB (operands[2]);
+ int me = extract_ME (operands[2]);
+ operands[3] = GEN_INT (me + 1);
+ operands[5] = GEN_INT (32 - (me + 1));
+ operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
+}"
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "*andsi3_internal5"
+ [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+ (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
+ (match_operand:SI 1 "mask_operand_wrap" ""))
+ (const_int 0)))
+ (clobber (match_scratch:SI 3 "=r,r"))]
+ "TARGET_POWERPC64"
+ "#"
+ "TARGET_POWERPC64"
+ [(parallel [(set (match_dup 2)
+ (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
+ (match_dup 5))
+ (const_int 0)))
+ (clobber (match_dup 3))])]
+ "
+{
+ int mb = extract_MB (operands[1]);
+ int me = extract_ME (operands[1]);
+ operands[4] = GEN_INT (me + 1);
+ operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
+}"
+ [(set_attr "type" "delayed_compare,compare")
+ (set_attr "length" "4,8")])
+
+(define_insn_and_split "*andsi3_internal6"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
+ (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "mask_operand_wrap" ""))
+ (const_int 0)))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (and:SI (match_dup 1)
+ (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "#"
+ "TARGET_POWERPC64"
+ [(parallel [(set (match_dup 3)
+ (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
+ (match_dup 5))
+ (const_int 0)))
+ (set (match_dup 0)
+ (and:SI (rotate:SI (match_dup 1) (match_dup 4))
+ (match_dup 5)))])
+ (set (match_dup 0)
+ (rotate:SI (match_dup 0) (match_dup 6)))]
+ "
+{
+ int mb = extract_MB (operands[2]);
+ int me = extract_ME (operands[2]);
+ operands[4] = GEN_INT (me + 1);
+ operands[6] = GEN_INT (32 - (me + 1));
+ operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
+}"
+ [(set_attr "type" "delayed_compare,compare")
+ (set_attr "length" "8,12")])
+
(define_expand "iorsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -3694,7 +3773,7 @@
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
#"
@@ -3707,7 +3786,7 @@
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 3)
(rotate:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
@@ -3722,7 +3801,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(rotate:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
#"
@@ -3736,7 +3815,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(rotate:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(rotate:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
@@ -3748,7 +3827,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
- (match_operand:SI 3 "mask_operand" "T")))]
+ (match_operand:SI 3 "mask_operand" "")))]
""
"{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
@@ -3757,10 +3836,10 @@
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
#"
@@ -3775,7 +3854,7 @@
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 4)
(and:SI (rotate:SI (match_dup 1)
(match_dup 2))
@@ -3790,11 +3869,11 @@
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
#"
@@ -3810,7 +3889,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
@@ -4128,7 +4207,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "T")))]
+ (match_operand:SI 3 "mask_operand" "")))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
@@ -4137,10 +4216,10 @@
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
+ "includes_lshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
#"
@@ -4155,7 +4234,7 @@
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_lshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 4)
(and:SI (ashift:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
@@ -4169,11 +4248,11 @@
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
+ "includes_lshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
#"
@@ -4189,7 +4268,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_lshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 0)
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
@@ -4367,7 +4446,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "T")))]
+ (match_operand:SI 3 "mask_operand" "")))]
"includes_rshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
@@ -4376,10 +4455,10 @@
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
+ "includes_rshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
#"
@@ -4394,7 +4473,7 @@
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_rshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 4)
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
@@ -4408,11 +4487,11 @@
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
+ "includes_rshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
#"
@@ -4428,7 +4507,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_rshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 0)
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)