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Fix x86-64 versus SSE builtins
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, patches at x86-64 dot org, rth at cygnus dot com
- Date: Thu, 7 Feb 2002 16:51:37 +0100
- Subject: Fix x86-64 versus SSE builtins
Hi,
this patch solves the crash on x86-64 that happends anytime you try to use
SSE builtins. It adds support to classify_argument for the new types as well
as fixes some other bugs around.
Bootstrapped/regtested i386.
Thu Feb 7 16:47:06 CET 2002 Jan Hubicka <jh@suse.cz>
* i386.c (classify_argument): Properly classify SSE/MMX modes and VOIDmode.
(construct_container): Fix handling of SSE operands.
(ix86_expand_builtin): Fix handling of 64bit pointers.
(mmx_maskmovq_rex): New pattern.
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.360
diff -c -3 -p -r1.360 i386.c
*** i386.c 2002/02/07 11:18:32 1.360
--- i386.c 2002/02/07 15:49:06
*************** classify_argument (mode, type, classes,
*** 1819,1825 ****
--- 1819,1837 ----
case SCmode:
classes[0] = X86_64_SSE_CLASS;
return 1;
+ case V4SFmode:
+ case V4SImode:
+ classes[0] = X86_64_SSE_CLASS;
+ classes[1] = X86_64_SSEUP_CLASS;
+ return 2;
+ case V2SFmode:
+ case V2SImode:
+ case V4HImode:
+ case V8QImode:
+ classes[0] = X86_64_SSE_CLASS;
+ return 1;
case BLKmode:
+ case VOIDmode:
return 0;
default:
abort ();
*************** construct_container (mode, type, in_retu
*** 1932,1938 ****
abort ();
}
if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS)
! return gen_rtx_REG (TImode, SSE_REGNO (sse_regno));
if (n == 2
&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
return gen_rtx_REG (TFmode, FIRST_STACK_REG);
--- 1944,1950 ----
abort ();
}
if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS)
! return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
if (n == 2
&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
return gen_rtx_REG (TFmode, FIRST_STACK_REG);
*************** ix86_expand_builtin (exp, target, subtar
*** 11661,11667 ****
return target;
case IX86_BUILTIN_MASKMOVQ:
! icode = CODE_FOR_mmx_maskmovq;
/* Note the arg order is different from the operand order. */
arg1 = TREE_VALUE (arglist);
arg2 = TREE_VALUE (TREE_CHAIN (arglist));
--- 11673,11679 ----
return target;
case IX86_BUILTIN_MASKMOVQ:
! icode = TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex : CODE_FOR_mmx_maskmovq;
/* Note the arg order is different from the operand order. */
arg1 = TREE_VALUE (arglist);
arg2 = TREE_VALUE (TREE_CHAIN (arglist));
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.333
diff -c -3 -p -r1.333 i386.md
*** i386.md 2002/02/04 09:48:34 1.333
--- i386.md 2002/02/07 15:49:15
***************
*** 17949,17955 ****
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
(match_operand:V8QI 2 "register_operand" "y")] 32))]
! "TARGET_SSE || TARGET_3DNOW_A"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
[(set_attr "type" "sse")])
--- 17949,17964 ----
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
(match_operand:V8QI 2 "register_operand" "y")] 32))]
! "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
! ;; @@@ check ordering of operands in intel/nonintel syntax
! "maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "sse")])
!
! (define_insn "mmx_maskmovq_rex"
! [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
! (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
! (match_operand:V8QI 2 "register_operand" "y")] 32))]
! "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
[(set_attr "type" "sse")])