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Re: sparc64 again
- From: DJ Delorie <dj at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 1 Feb 2002 13:55:59 -0500
- Subject: Re: sparc64 again
- References: <200201282159.g0SLxg728050@greed.delorie.com>
> The last change I made was needed but not complete.
Nor, apparently, was that one, since that function is called from one
other place that does not try to allocate the extra registers. This
is what it looks like now. Comments?
2002-02-01 DJ Delorie <dj@redhat.com>
* config/sparc/sparc.c (sparc_emit_set_symbolic_const64): If
we are given conflicting registers, switch to the other one we
had allocated for us.
* config/sparc/sparc.md (reload_indi, reload_outdi): Pass op[2]
as TImode so we know when the "other" register is available.
Index: sparc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.c,v
retrieving revision 1.179
diff -p -3 -r1.179 sparc.c
*** sparc.c 2002/01/26 02:09:02 1.179
--- sparc.c 2002/02/01 18:54:50
*************** sparc_emit_set_symbolic_const64 (op0, op
*** 1366,1371 ****
--- 1366,1379 ----
rtx op1;
rtx temp1;
{
+ rtx ti_temp1 = 0;
+
+ if (temp1 && GET_MODE (temp1) == TImode)
+ {
+ ti_temp1 = temp1;
+ temp1 = gen_rtx_REG (DImode, REGNO (temp1));
+ }
+
switch (sparc_cmodel)
{
case CM_MEDLOW:
*************** sparc_emit_set_symbolic_const64 (op0, op
*** 1419,1430 ****
sllx %temp3, 32, %temp5
or %temp4, %temp5, %reg */
! /* Getting this right wrt. reloading is really tricky.
! We _MUST_ have a separate temporary at this point,
! if we don't barf immediately instead of generating
! incorrect code. */
if (rtx_equal_p (temp1, op0))
! abort ();
emit_insn (gen_sethh (op0, op1));
emit_insn (gen_setlm (temp1, op1));
--- 1427,1442 ----
sllx %temp3, 32, %temp5
or %temp4, %temp5, %reg */
! /* It is possible that one of the registers we got for operands[2]
! might coincide with that of operands[0] (which is why we made
! it TImode). Pick the other one to use as our scratch. */
if (rtx_equal_p (temp1, op0))
! {
! if (ti_temp1)
! temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
! else
! abort();
! }
emit_insn (gen_sethh (op0, op1));
emit_insn (gen_setlm (temp1, op1));
*************** sparc_emit_set_symbolic_const64 (op0, op
*** 1462,1473 ****
}
else
{
! /* Getting this right wrt. reloading is really tricky.
! We _MUST_ have a separate temporary at this point,
! so we barf immediately instead of generating
! incorrect code. */
! if (temp1 == op0)
! abort ();
emit_insn (gen_embmedany_textuhi (op0, op1));
emit_insn (gen_embmedany_texthi (temp1, op1));
--- 1474,1489 ----
}
else
{
! /* It is possible that one of the registers we got for operands[2]
! might coincide with that of operands[0] (which is why we made
! it TImode). Pick the other one to use as our scratch. */
! if (rtx_equal_p (temp1, op0))
! {
! if (ti_temp1)
! temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1);
! else
! abort();
! }
emit_insn (gen_embmedany_textuhi (op0, op1));
emit_insn (gen_embmedany_texthi (temp1, op1));
Index: sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.144
diff -p -3 -r1.144 sparc.md
*** sparc.md 2002/01/24 10:42:55 1.144
--- sparc.md 2002/02/01 18:54:51
***************
*** 2734,2741 ****
&& ! flag_pic"
"
{
! sparc_emit_set_symbolic_const64 (operands[0], operands[1],
! gen_rtx_REG (DImode, REGNO (operands[2])));
DONE;
}")
--- 2734,2740 ----
&& ! flag_pic"
"
{
! sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
DONE;
}")
***************
*** 2748,2755 ****
&& ! flag_pic"
"
{
! sparc_emit_set_symbolic_const64 (operands[0], operands[1],
! gen_rtx_REG (DImode, REGNO (operands[2])));
DONE;
}")
--- 2747,2753 ----
&& ! flag_pic"
"
{
! sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
DONE;
}")