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Re: new macro STARTING_FRAME_PHASE: alignment

| Of course, the biggest problem with this is that cache line size is a
| property of the processor, not of the ISA, and so all this probably
| breaks on IBM's POWER chips with a 64-byte cache line size.  However
| the likelihood of a problem is very small, unless you start making
| arrays of wait_nodes.

	FYI, the cache lines on 64-bit PowerPC implementations is 128
bytes, not 64 bytes.

David
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