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alpha extendsidi tweak
- From: Richard Henderson <rth at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 10 Jan 2002 00:54:36 -0800
- Subject: alpha extendsidi tweak
Best case truncating a 64-bit value to a 32-bit sign-extended
value with just floating point registers is
cvtql in, tmp
cvtlq tmp, out
each with a latency of 4 cycles. Best case with an intermediate
integer register is
ftoit in, tmp
addl tmp, 0, tmp
itoft tmp, out
with latencies 3,1,3 respectively. So without regard to register
pressure, we've saved one cycle. Unfortunately, the 8 cycle case
above isn't easy to get. We would have to do it via peepholes
which don't show up that often. What we more often get is
ftoit in, t1
itofs t1, t2
cvtlq t2, out
for a total of 10 cycles.
The following appears to coerce reload to choose the 7 cycle
sequence more often.
r~
* config/alpha/alpha.md (extendsidi2_fix): Penalize f/f alternative.
Index: alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.173
diff -c -p -d -u -r1.173 alpha.md
--- alpha.md 2002/01/10 02:07:46 1.173
+++ alpha.md 2002/01/10 04:23:19
@@ -460,7 +460,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
(set_attr "length" "*,*,*,8")])
(define_insn "*extendsidi2_fix"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
(sign_extend:DI
(match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
"TARGET_FIX"