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PATCH: Darwin-specific bug fix
- From: Dale Johannesen <dalej at apple dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 6 Jan 2002 11:52:15 -0800
- Subject: PATCH: Darwin-specific bug fix
My previous patch for Darwin-specific floating point constant optimization
overlooked that double consts could be put into two int regs. This
adds the missing pattern. Sorry. Bootstrapped and tested on Darwin.
Sun Jan 6 11:47:55 PST 2002 Dale Johannesen <dalej@apple.com>
* config/rs6000/rs6000.md: add missing int register target
case to movdf_low
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.151
diff -u -d -b -w -c -3 -p -r1.151 rs6000.md
cvs server: conflicting specifications of output style
*** rs6000.md 2001/12/26 18:02:17 1.151
--- rs6000.md 2002/01/06 19:33:26
***************
*** 7590,7602 ****
(set_attr "length" "4")])
(define_insn "movdf_low"
! [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
! "lfd %0,lo16(%2)(%1)"
[(set_attr "type" "load")
! (set_attr "length" "4")])
(define_insn "movdf_low_st"
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
--- 7590,7624 ----
(set_attr "length" "4")])
(define_insn "movdf_low"
! [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
! (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
! "*
! {
! switch (which_alternative)
! {
! case 0:
! return \"lfd %0,lo16(%2)(%1)\";
! case 1:
! {
! rtx operands2[4];
! operands2[0] = operands[0];
! operands2[1] = operands[1];
! operands2[2] = operands[2];
! operands2[3] = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
! output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
! /* We cannot rely on ha16(low half)==ha16(high half), alas,
! although in practice it almost always is. */
! output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
! return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
! }
! default:
! abort();
! }
! }"
[(set_attr "type" "load")
! (set_attr "length" "4,12")])
(define_insn "movdf_low_st"
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b")