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[RFC] PowerPC prefetch
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: dalej at apple dot com, Geoff Keating <geoffk at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org, Stan Shebs <shebs at apple dot com>
- Date: Tue, 18 Dec 2001 16:25:09 -0500
- Subject: [RFC] PowerPC prefetch
Does this look like the correct implementation of the prefetch
pattern for PowerPC?
If the pattern could actually see the MEM, we could handle loops
better by using the two operands to dcbt for the base+index addressing.
Thanks, David
* rs6000.md (prefetch): New pattern.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.148
diff -c -p -r1.148 rs6000.md
*** rs6000.md 2001/12/17 19:11:11 1.148
--- rs6000.md 2001/12/18 21:20:07
***************
*** 13819,13824 ****
--- 13819,13835 ----
DONE;
}")
+ (define_insn "prefetch"
+ [(prefetch (match_operand:DI 0 "address_operand" "p")
+ (match_operand:DI 1 "const_int_operand" "n")
+ (match_operand:DI 2 "const_int_operand" "n"))]
+ "TARGET_POWERPC"
+ "*
+ {
+ return INTVAL (operands[1]) ? \"dcbst 0,%0\" : \"dcbt 0,%0\";
+ }"
+ [(set_attr "type" "load")])
+
;; AltiVec patterns
;; Generic LVX load instruction.