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Re: Vector subregs

From: Jan Hubicka <jh at suse dot cz>
To: Alexandre Oliva <aoliva at redhat dot com>
Cc: Dale Johannesen <dalej at apple dot com>, gcc-patches at gcc dot gnu dot org, gcc at gcc dot gnu dot org
Date: Fri, 14 Dec 2001 21:34:33 +0100
Subject: Re: Vector subregs
References: <93A5FF64-F0C2-11D5-86F6-003065C86F94@apple.com> <orheqt4oh0.fsf@free.redhat.lsd.ic.unicamp.br>

> On Dec 14, 2001, Dale Johannesen <dalej@apple.com> wrote:
> 
> > Subreg's of vectors don't have a register implementation on any
> > hardware AFAIK, so there is no reason to support them.
> 
> Hmm...  The SH4 can use 4 FP registers as a V4SF unit for some
> operations, as well as 4 of these sets as a 4x4 SF matrix.  I suppose
> it would be reasonable to be able to use subregs to refer to
> individual registers that compose such vectors and matrices, wouldn't
> it?
Similar case is thinkable even for x86, that can do number of scalar
oprerations in SSE and given the register pressure it is quite desirable
to teach gcc using SSE for scalar integer arithmetics if all operations needed
are supported.
Then moving between (subreg:SI (vector) 0) may make sense too.

Honza
> 
> -- 
> Alexandre Oliva   Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
> Red Hat GCC Developer                  aoliva@{cygnus.com, redhat.com}
> CS PhD student at IC-Unicamp        oliva@{lsd.ic.unicamp.br, gnu.org}
> Free Software Evangelist    *Please* write to mailing lists, not to me

References:
- Vector subregs
  - From: Dale Johannesen
- Re: Vector subregs
  - From: Alexandre Oliva

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