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[PATCH]: Updated 7450 patch
- From: Daniel Berlin <dan at cgsoftware dot com>
- To: <gcc-patches at gcc dot gnu dot org>
- Cc: <dje at watson dot ibm dot com>, <aldyh at redhat dot com>
- Date: Fri, 30 Nov 2001 17:29:07 -0500 (EST)
- Subject: [PATCH]: Updated 7450 patch
I noticed that the 7450 was missing from the -mcpu handling switch, so we
never passed -mppc to the assembler command line if you did -mcpu=7450.
It also never added -D_ARCH_PPC for mcpu=7450.
This looks like a simple oversight by whoever added the 7450. It would
also mean that -maltivec -mcpu=7450 wouldn't work, because the assembler
doesn't like -maltivec without -mppc.
So I fixed it.
In addition, i removed more unspecs, renamed more patterns, and added the
builtins for loading the other vector types, as Aldy asked me to.
I also updated the test to take into account the renamed function.
I'll add more to the test in a seperate patch, after i finish the rest of
the builtins.
Hopefully, this is still okay by everyone.
It bootstraps on powerpc-linux-gnu, no regressions.
2001-11-29 Daniel Berlin <dan@cgsoftware.com>
* config/rs6000/rs6000.c (altivec_expand_builtin): add
ALTIVEC_BUILTIN_LD_INTERNAL_4sf and ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
*_16qi,_8hi, rename existing V4SI ones to *_4si.
(altivec_init_builtins): Ditto.
(bdesc_2arg): Rename CODE_FOR_* to match changes in MD file.
* config/rs6000/rs6000.md: Add attribute types vecsimple,
veccomplex, vecfloat, and vecperm, for altivec instructions.
Modify altivec patterns to use approriate attribute type.
Modify altivec patterns to match RTL operations where approriate
(IE no unspec where we can avoid it).
Add vector unit scheduling for ppc7450.
Rename patterns to what they are where approriate
(altivec_vaddfp->addv4sf3, etc)
* config/rs6000/rs6000.h (enum rs6000_builtins): Change VRS->VSR.
Pass -mppc, and define _ARCH_PPC, if -mcpu=7450 is used.
* config/rs6000/sysv4.h: Add -mcpu=7450.
* testsuite/gcc.dg/altivec-1.c: Update test to take into account renamed
_builtin_altivec_ld_interal function.
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.245
diff -c -3 -p -w -B -b -r1.245 rs6000.c
*** rs6000.c 2001/11/30 02:04:23 1.245
--- rs6000.c 2001/11/30 22:23:32
*************** struct builtin_description
*** 2976,2985 ****
/* Simple binary operatiors: VECc = foo (VECa, VECb). */
static const struct builtin_description bdesc_2arg[] =
{
! { MASK_ALTIVEC, CODE_FOR_altivec_vaddubm, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
! { MASK_ALTIVEC, CODE_FOR_altivec_vadduhm, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
! { MASK_ALTIVEC, CODE_FOR_altivec_vadduwm, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
! { MASK_ALTIVEC, CODE_FOR_altivec_vaddfp, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
--- 2976,2985 ----
/* Simple binary operatiors: VECc = foo (VECa, VECb). */
static const struct builtin_description bdesc_2arg[] =
{
! { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
! { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
! { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
! { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
*************** static const struct builtin_description
*** 2987,2993 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
! { MASK_ALTIVEC, CODE_FOR_altivec_vand, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
{ MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
--- 2987,2993 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
! { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
{ MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
*************** static const struct builtin_description
*** 3008,3033 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxub, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsb, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuh, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsh, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuw, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsw, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxfp, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminub, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminsb, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminuh, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminsh, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminuw, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminsw, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vminfp, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
--- 3008,3033 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
! { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
! { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
! { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
! { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
! { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
! { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
! { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
! { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
! { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
! { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
! { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
! { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
! { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
! { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
*************** static const struct builtin_description
*** 3037,3043 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
! { MASK_ALTIVEC, CODE_FOR_altivec_vor, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
--- 3037,3043 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
! { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
*************** static const struct builtin_description
*** 3058,3074 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
{ MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vrsh, "__builtin_altivec_vrsh", ALTIVEC_BUILTIN_VRSH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vrsw, "__builtin_altivec_vrsw", ALTIVEC_BUILTIN_VRSW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsububm, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhm, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsubuwm, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsubfp, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
--- 3058,3074 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
{ MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
! { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
! { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
! { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
! { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
*************** static const struct builtin_description
*** 3081,3087 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
! { MASK_ALTIVEC, CODE_FOR_altivec_vxor, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
};
static rtx
--- 3081,3087 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
! { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
};
static rtx
*************** altivec_expand_builtin (exp, target)
*** 3134,3141 ****
switch (fcode)
{
! case ALTIVEC_BUILTIN_LD_INTERNAL:
! icode = CODE_FOR_altivec_lvx;
arg0 = TREE_VALUE (arglist);
op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
tmode = insn_data[icode].operand[0].mode;
--- 3134,3141 ----
switch (fcode)
{
! case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
! icode = CODE_FOR_altivec_lvx_16qi;
arg0 = TREE_VALUE (arglist);
op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
tmode = insn_data[icode].operand[0].mode;
*************** altivec_expand_builtin (exp, target)
*** 3154,3163 ****
return 0;
emit_insn (pat);
return target;
! case ALTIVEC_BUILTIN_ST_INTERNAL:
! icode = CODE_FOR_altivec_stvx;
arg0 = TREE_VALUE (arglist);
arg1 = TREE_VALUE (TREE_CHAIN (arglist));
op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
--- 3154,3223 ----
return 0;
emit_insn (pat);
return target;
+ case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
+ icode = CODE_FOR_altivec_lvx_8hi;
+ arg0 = TREE_VALUE (arglist);
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ tmode = insn_data[icode].operand[0].mode;
+ mode0 = insn_data[icode].operand[1].mode;
! if (! target
! || GET_MODE (target) != tmode
! || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
! target = gen_reg_rtx (tmode);
!
! if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
! op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
!
! pat = GEN_FCN (icode) (target, op0);
! if (! pat)
! return 0;
! emit_insn (pat);
! return target;
! case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
! icode = CODE_FOR_altivec_lvx_4si;
arg0 = TREE_VALUE (arglist);
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ tmode = insn_data[icode].operand[0].mode;
+ mode0 = insn_data[icode].operand[1].mode;
+
+ if (! target
+ || GET_MODE (target) != tmode
+ || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
+ target = gen_reg_rtx (tmode);
+
+ if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
+ op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
+
+ pat = GEN_FCN (icode) (target, op0);
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+ return target;
+ case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
+ icode = CODE_FOR_altivec_lvx_4sf;
+ arg0 = TREE_VALUE (arglist);
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ tmode = insn_data[icode].operand[0].mode;
+ mode0 = insn_data[icode].operand[1].mode;
+
+ if (! target
+ || GET_MODE (target) != tmode
+ || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
+ target = gen_reg_rtx (tmode);
+
+ if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
+ op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
+
+ pat = GEN_FCN (icode) (target, op0);
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+ return target;
+
+ case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
+ icode = CODE_FOR_altivec_stvx_16qi;
+ arg0 = TREE_VALUE (arglist);
arg1 = TREE_VALUE (TREE_CHAIN (arglist));
op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
*************** altivec_expand_builtin (exp, target)
*** 3174,3179 ****
--- 3234,3296 ----
return 0;
emit_insn (pat);
return NULL_RTX;
+ case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
+ icode = CODE_FOR_altivec_stvx_8hi;
+ arg0 = TREE_VALUE (arglist);
+ arg1 = TREE_VALUE (TREE_CHAIN (arglist));
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+ mode0 = insn_data[icode].operand[0].mode;
+ mode1 = insn_data[icode].operand[1].mode;
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
+ if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
+ op1 = copy_to_mode_reg (mode1, op1);
+
+ pat = GEN_FCN (icode) (op0, op1);
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+ return NULL_RTX;
+ case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
+ icode = CODE_FOR_altivec_stvx_4si;
+ arg0 = TREE_VALUE (arglist);
+ arg1 = TREE_VALUE (TREE_CHAIN (arglist));
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+ mode0 = insn_data[icode].operand[0].mode;
+ mode1 = insn_data[icode].operand[1].mode;
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
+ if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
+ op1 = copy_to_mode_reg (mode1, op1);
+
+ pat = GEN_FCN (icode) (op0, op1);
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+ return NULL_RTX;
+ case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
+ icode = CODE_FOR_altivec_stvx_4sf;
+ arg0 = TREE_VALUE (arglist);
+ arg1 = TREE_VALUE (TREE_CHAIN (arglist));
+ op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+ mode0 = insn_data[icode].operand[0].mode;
+ mode1 = insn_data[icode].operand[1].mode;
+
+ if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
+ op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
+ if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
+ op1 = copy_to_mode_reg (mode1, op1);
+
+ pat = GEN_FCN (icode) (op0, op1);
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+ return NULL_RTX;
}
/* Handle simple binary operations. */
*************** altivec_init_builtins (void)
*** 3223,3233 ****
--- 3340,3365 ----
tree endlink = void_list_node;
tree pint_type_node = build_pointer_type (integer_type_node);
+ tree pshort_type_node = build_pointer_type (short_integer_type_node);
+ tree pchar_type_node = build_pointer_type (char_type_node);
+ tree pfloat_type_node = build_pointer_type (float_type_node);
/* V4SI foo (int *). */
tree v4si_ftype_pint
= build_function_type (V4SI_type_node,
tree_cons (NULL_TREE, pint_type_node, endlink));
+ /* V8HI foo (short *). */
+ tree v8hi_ftype_pshort
+ = build_function_type (V8HI_type_node,
+ tree_cons (NULL_TREE, pshort_type_node, endlink));
+ /* V16QI foo (char *). */
+ tree v16qi_ftype_pchar
+ = build_function_type (V16QI_type_node,
+ tree_cons (NULL_TREE, pchar_type_node, endlink));
+ /* V4SF foo (float *). */
+ tree v4sf_ftype_pfloat
+ = build_function_type (V4SF_type_node,
+ tree_cons (NULL_TREE, pfloat_type_node, endlink));
/* void foo (int *, V4SI). */
tree void_ftype_pint_v4si
*************** altivec_init_builtins (void)
*** 3235,3240 ****
--- 3367,3390 ----
tree_cons (NULL_TREE, pint_type_node,
tree_cons (NULL_TREE, V4SI_type_node,
endlink)));
+ /* void foo (short *, V8HI). */
+ tree void_ftype_pshort_v8hi
+ = build_function_type (void_type_node,
+ tree_cons (NULL_TREE, pshort_type_node,
+ tree_cons (NULL_TREE, V8HI_type_node,
+ endlink)));
+ /* void foo (char *, V16QI). */
+ tree void_ftype_pchar_v16qi
+ = build_function_type (void_type_node,
+ tree_cons (NULL_TREE, pchar_type_node,
+ tree_cons (NULL_TREE, V16QI_type_node,
+ endlink)));
+ /* void foo (float *, V4SF). */
+ tree void_ftype_pfloat_v4sf
+ = build_function_type (void_type_node,
+ tree_cons (NULL_TREE, pfloat_type_node,
+ tree_cons (NULL_TREE, V4SF_type_node,
+ endlink)));
tree v4si_ftype_v4si_v4si
= build_function_type (V4SI_type_node,
*************** altivec_init_builtins (void)
*** 3326,3333 ****
tree_cons (NULL_TREE, V8HI_type_node,
endlink)));
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL);
/* Add the simple binary operators. */
d = (struct builtin_description *) bdesc_2arg;
--- 3476,3489 ----
tree_cons (NULL_TREE, V8HI_type_node,
endlink)));
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
! def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
/* Add the simple binary operators. */
d = (struct builtin_description *) bdesc_2arg;
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.143
diff -c -3 -p -w -B -b -r1.143 rs6000.h
*** rs6000.h 2001/11/22 02:19:56 1.143
--- rs6000.h 2001/11/30 22:23:34
*************** Boston, MA 02111-1307, USA. */
*** 76,81 ****
--- 76,82 ----
%{mcpu=604e: -D_ARCH_PPC} \
%{mcpu=620: -D_ARCH_PPC} \
%{mcpu=740: -D_ARCH_PPC} \
+ %{mcpu=7450: -D_ARCH_PPC} \
%{mcpu=750: -D_ARCH_PPC} \
%{mcpu=801: -D_ARCH_PPC} \
%{mcpu=821: -D_ARCH_PPC} \
*************** Boston, MA 02111-1307, USA. */
*** 113,118 ****
--- 114,120 ----
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc} \
%{mcpu=740: -mppc} \
+ %{mcpu=7450: -mppc} \
%{mcpu=750: -mppc} \
%{mcpu=801: -mppc} \
%{mcpu=821: -mppc} \
*************** extern int frame_pointer_needed;
*** 2829,2836 ****
enum rs6000_builtins
{
/* AltiVec builtins. */
! ALTIVEC_BUILTIN_ST_INTERNAL,
! ALTIVEC_BUILTIN_LD_INTERNAL,
ALTIVEC_BUILTIN_VADDUBM,
ALTIVEC_BUILTIN_VADDUHM,
ALTIVEC_BUILTIN_VADDUWM,
--- 2831,2844 ----
enum rs6000_builtins
{
/* AltiVec builtins. */
! ALTIVEC_BUILTIN_ST_INTERNAL_4si,
! ALTIVEC_BUILTIN_LD_INTERNAL_4si,
! ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
! ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
! ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
! ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
! ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
! ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
ALTIVEC_BUILTIN_VADDUBM,
ALTIVEC_BUILTIN_VADDUHM,
ALTIVEC_BUILTIN_VADDUWM,
*************** enum rs6000_builtins
*** 2913,2920 ****
ALTIVEC_BUILTIN_VSL,
ALTIVEC_BUILTIN_VSLO,
ALTIVEC_BUILTIN_VSRB,
! ALTIVEC_BUILTIN_VRSH,
! ALTIVEC_BUILTIN_VRSW,
ALTIVEC_BUILTIN_VSRAB,
ALTIVEC_BUILTIN_VSRAH,
ALTIVEC_BUILTIN_VSRAW,
--- 2921,2928 ----
ALTIVEC_BUILTIN_VSL,
ALTIVEC_BUILTIN_VSLO,
ALTIVEC_BUILTIN_VSRB,
! ALTIVEC_BUILTIN_VSRH,
! ALTIVEC_BUILTIN_VSRW,
ALTIVEC_BUILTIN_VSRAB,
ALTIVEC_BUILTIN_VSRAH,
ALTIVEC_BUILTIN_VSRAW,
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.140
diff -c -3 -p -w -B -b -r1.140 rs6000.md
*** rs6000.md 2001/11/24 06:44:11 1.140
--- rs6000.md 2001/11/30 22:23:35
***************
*** 37,43 ****
;; Define an insn type attribute. This is used in function unit delay
;; computations.
! (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,altivec"
(const_string "integer"))
;; Length (in bytes).
--- 37,43 ----
;; Define an insn type attribute. This is used in function unit delay
;; computations.
! (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec"
(const_string "integer"))
;; Length (in bytes).
***************
*** 70,76 ****
2 1)
(define_function_unit "lsu" 1 0
! (and (eq_attr "type" "load")
(eq_attr "cpu" "ppc7450"))
3 1)
--- 70,76 ----
2 1)
(define_function_unit "lsu" 1 0
! (and (eq_attr "type" "load,vecload")
(eq_attr "cpu" "ppc7450"))
3 1)
***************
*** 85,91 ****
2 1)
(define_function_unit "lsu" 1 0
! (and (eq_attr "type" "store")
(eq_attr "cpu" "ppc7450"))
3 1)
--- 85,91 ----
2 1)
(define_function_unit "lsu" 1 0
! (and (eq_attr "type" "store,vecstore")
(eq_attr "cpu" "ppc7450"))
3 1)
***************
*** 317,322 ****
--- 317,342 ----
(and (eq_attr "type" "cr_logical")
(eq_attr "cpu" "ppc7450"))
1 1)
+ (define_function_unit "viu1" 1 0
+ (and (eq_attr "type" "vecsimple")
+ (eq_attr "cpu" "ppc7450"))
+ 1 1)
+ (define_function_unit "viu2" 1 0
+ (and (eq_attr "type" "veccomplex")
+ (eq_attr "cpu" "ppc7450"))
+ 4 1)
+ (define_function_unit "vfpu" 1 0
+ (and (eq_attr "type" "veccmp")
+ (eq_attr "cpu" "ppc7450"))
+ 2 1)
+ (define_function_unit "vfpu" 1 0
+ (and (eq_attr "type" "vecfloat")
+ (eq_attr "cpu" "ppc7450"))
+ 4 1)
+ (define_function_unit "vpu" 1 0
+ (and (eq_attr "type" "vecperm")
+ (eq_attr "cpu" "ppc7450"))
+ 2 1)
; PPC750 has two integer units: a primary one which can perform all
; operations and a secondary one which is fed in lock step with the first
***************
*** 13559,13579 ****
;; AltiVec patterns
;; Generic LVX load instruction.
! (define_insn "altivec_lvx"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
! [(set_attr "type" "altivec")])
;; Generic STVX store instruction.
! (define_insn "altivec_stvx"
[(set (match_operand:V4SI 0 "memory_operand" "=m")
(match_operand:V4SI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
! [(set_attr "type" "altivec")])
;; Vector move instructions.
(define_expand "movv4si"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "")
--- 13579,13641 ----
;; AltiVec patterns
;; Generic LVX load instruction.
! (define_insn "altivec_lvx_4si"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
! [(set_attr "type" "vecload")])
!
! (define_insn "altivec_lvx_8hi"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (match_operand:V8HI 1 "memory_operand" "m"))]
! "TARGET_ALTIVEC"
! "lvx %0,%y1"
! [(set_attr "type" "vecload")])
+ (define_insn "altivec_lvx_16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (match_operand:V16QI 1 "memory_operand" "m"))]
+ "TARGET_ALTIVEC"
+ "lvx %0,%y1"
+ [(set_attr "type" "vecload")])
+
+ (define_insn "altivec_lvx_4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=v")
+ (match_operand:V4SF 1 "memory_operand" "m"))]
+ "TARGET_ALTIVEC"
+ "lvx %0,%y1"
+ [(set_attr "type" "vecload")])
+
;; Generic STVX store instruction.
! (define_insn "altivec_stvx_4si"
[(set (match_operand:V4SI 0 "memory_operand" "=m")
(match_operand:V4SI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "altivec_stvx_8hi"
! [(set (match_operand:V8HI 0 "memory_operand" "=m")
! (match_operand:V8HI 1 "register_operand" "v"))]
! "TARGET_ALTIVEC"
! "stvx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "altivec_stvx_16qi"
! [(set (match_operand:V16QI 0 "memory_operand" "=m")
! (match_operand:V16QI 1 "register_operand" "v"))]
! "TARGET_ALTIVEC"
! "stvx %1,%y0"
! [(set_attr "type" "vecstore")])
+ (define_insn "altivec_stvx_4sf"
+ [(set (match_operand:V4SF 0 "memory_operand" "=m")
+ (match_operand:V4SF 1 "register_operand" "v"))]
+ "TARGET_ALTIVEC"
+ "stvx %1,%y0"
+ [(set_attr "type" "vecstore")])
+
;; Vector move instructions.
(define_expand "movv4si"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "")
***************
*** 13666,13702 ****
;; Simple binary operations.
! (define_insn "altivec_vaddubm"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 31))]
"TARGET_ALTIVEC"
"vaddubm %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vadduhm"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 32))]
"TARGET_ALTIVEC"
"vadduhm %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vadduwm"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 33))]
"TARGET_ALTIVEC"
"vadduwm %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vaddfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")] 34))]
"TARGET_ALTIVEC"
"vaddfp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vaddcuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13728,13764 ----
;; Simple binary operations.
! (define_insn "addv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vaddubm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "addv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vadduhm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "addv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vadduwm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "addv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vaddfp %0,%1,%2"
! [(set_attr "type" "vecfloat")])
(define_insn "altivec_vaddcuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13704,13710 ****
(match_operand:V4SI 2 "register_operand" "v")] 35))]
"TARGET_ALTIVEC"
"vaddcuw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vaddubs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13766,13772 ----
(match_operand:V4SI 2 "register_operand" "v")] 35))]
"TARGET_ALTIVEC"
"vaddcuw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddubs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13712,13718 ****
(match_operand:V16QI 2 "register_operand" "v")] 36))]
"TARGET_ALTIVEC"
"vaddubs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vaddsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13774,13780 ----
(match_operand:V16QI 2 "register_operand" "v")] 36))]
"TARGET_ALTIVEC"
"vaddubs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13720,13726 ****
(match_operand:V16QI 2 "register_operand" "v")] 37))]
"TARGET_ALTIVEC"
"vaddsbs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vadduhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13782,13788 ----
(match_operand:V16QI 2 "register_operand" "v")] 37))]
"TARGET_ALTIVEC"
"vaddsbs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vadduhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13728,13734 ****
(match_operand:V8HI 2 "register_operand" "v")] 38))]
"TARGET_ALTIVEC"
"vadduhs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vaddshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13790,13796 ----
(match_operand:V8HI 2 "register_operand" "v")] 38))]
"TARGET_ALTIVEC"
"vadduhs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13736,13742 ****
(match_operand:V8HI 2 "register_operand" "v")] 39))]
"TARGET_ALTIVEC"
"vaddshs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vadduws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13798,13804 ----
(match_operand:V8HI 2 "register_operand" "v")] 39))]
"TARGET_ALTIVEC"
"vaddshs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vadduws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13744,13750 ****
(match_operand:V4SI 2 "register_operand" "v")] 40))]
"TARGET_ALTIVEC"
"vadduws %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vaddsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13806,13812 ----
(match_operand:V4SI 2 "register_operand" "v")] 40))]
"TARGET_ALTIVEC"
"vadduws %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vaddsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13752,13766 ****
(match_operand:V4SI 2 "register_operand" "v")] 41))]
"TARGET_ALTIVEC"
"vaddsws %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vand"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 42))]
"TARGET_ALTIVEC"
"vand %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vandc"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13814,13828 ----
(match_operand:V4SI 2 "register_operand" "v")] 41))]
"TARGET_ALTIVEC"
"vaddsws %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "andv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vand %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vandc"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13768,13774 ****
(match_operand:V4SI 2 "register_operand" "v")] 43))]
"TARGET_ALTIVEC"
"vandc %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vavgub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13830,13836 ----
(match_operand:V4SI 2 "register_operand" "v")] 43))]
"TARGET_ALTIVEC"
"vandc %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vavgub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13776,13782 ****
(match_operand:V16QI 2 "register_operand" "v")] 44))]
"TARGET_ALTIVEC"
"vavgub %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vavgsb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13838,13844 ----
(match_operand:V16QI 2 "register_operand" "v")] 44))]
"TARGET_ALTIVEC"
"vavgub %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vavgsb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13784,13790 ****
(match_operand:V16QI 2 "register_operand" "v")] 45))]
"TARGET_ALTIVEC"
"vavgsb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vavguh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13846,13852 ----
(match_operand:V16QI 2 "register_operand" "v")] 45))]
"TARGET_ALTIVEC"
"vavgsb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vavguh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13792,13798 ****
(match_operand:V8HI 2 "register_operand" "v")] 46))]
"TARGET_ALTIVEC"
"vavguh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vavgsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13854,13860 ----
(match_operand:V8HI 2 "register_operand" "v")] 46))]
"TARGET_ALTIVEC"
"vavguh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vavgsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13800,13806 ****
(match_operand:V8HI 2 "register_operand" "v")] 47))]
"TARGET_ALTIVEC"
"vavgsh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vavguw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13862,13868 ----
(match_operand:V8HI 2 "register_operand" "v")] 47))]
"TARGET_ALTIVEC"
"vavgsh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vavguw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13808,13814 ****
(match_operand:V4SI 2 "register_operand" "v")] 48))]
"TARGET_ALTIVEC"
"vavguw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vavgsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13870,13876 ----
(match_operand:V4SI 2 "register_operand" "v")] 48))]
"TARGET_ALTIVEC"
"vavguw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vavgsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13816,13822 ****
(match_operand:V4SI 2 "register_operand" "v")] 49))]
"TARGET_ALTIVEC"
"vavgsw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpbfp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13878,13884 ----
(match_operand:V4SI 2 "register_operand" "v")] 49))]
"TARGET_ALTIVEC"
"vavgsw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpbfp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13824,13830 ****
(match_operand:V4SF 2 "register_operand" "v")] 50))]
"TARGET_ALTIVEC"
"vcmpbfp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13886,13892 ----
(match_operand:V4SF 2 "register_operand" "v")] 50))]
"TARGET_ALTIVEC"
"vcmpbfp %0,%1,%2"
! [(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpequb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13832,13838 ****
(match_operand:V16QI 2 "register_operand" "v")] 51))]
"TARGET_ALTIVEC"
"vcmpequb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13894,13900 ----
(match_operand:V16QI 2 "register_operand" "v")] 51))]
"TARGET_ALTIVEC"
"vcmpequb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpequh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13840,13846 ****
(match_operand:V8HI 2 "register_operand" "v")] 52))]
"TARGET_ALTIVEC"
"vcmpequh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpequw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13902,13908 ----
(match_operand:V8HI 2 "register_operand" "v")] 52))]
"TARGET_ALTIVEC"
"vcmpequh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpequw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13848,13854 ****
(match_operand:V4SI 2 "register_operand" "v")] 53))]
"TARGET_ALTIVEC"
"vcmpequw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpeqfp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13910,13916 ----
(match_operand:V4SI 2 "register_operand" "v")] 53))]
"TARGET_ALTIVEC"
"vcmpequw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpeqfp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13856,13862 ****
(match_operand:V4SF 2 "register_operand" "v")] 54))]
"TARGET_ALTIVEC"
"vcmpeqfp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgefp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13918,13924 ----
(match_operand:V4SF 2 "register_operand" "v")] 54))]
"TARGET_ALTIVEC"
"vcmpeqfp %0,%1,%2"
! [(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpgefp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13864,13870 ****
(match_operand:V4SF 2 "register_operand" "v")] 55))]
"TARGET_ALTIVEC"
"vcmpgefp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13926,13932 ----
(match_operand:V4SF 2 "register_operand" "v")] 55))]
"TARGET_ALTIVEC"
"vcmpgefp %0,%1,%2"
! [(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpgtub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13872,13878 ****
(match_operand:V16QI 2 "register_operand" "v")] 56))]
"TARGET_ALTIVEC"
"vcmpgtub %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13934,13940 ----
(match_operand:V16QI 2 "register_operand" "v")] 56))]
"TARGET_ALTIVEC"
"vcmpgtub %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpgtsb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13880,13886 ****
(match_operand:V16QI 2 "register_operand" "v")] 57))]
"TARGET_ALTIVEC"
"vcmpgtsb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13942,13948 ----
(match_operand:V16QI 2 "register_operand" "v")] 57))]
"TARGET_ALTIVEC"
"vcmpgtsb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpgtuh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13888,13894 ****
(match_operand:V8HI 2 "register_operand" "v")] 58))]
"TARGET_ALTIVEC"
"vcmpgtuh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 13950,13956 ----
(match_operand:V8HI 2 "register_operand" "v")] 58))]
"TARGET_ALTIVEC"
"vcmpgtuh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpgtsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13896,13902 ****
(match_operand:V8HI 2 "register_operand" "v")] 59))]
"TARGET_ALTIVEC"
"vcmpgtsh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13958,13964 ----
(match_operand:V8HI 2 "register_operand" "v")] 59))]
"TARGET_ALTIVEC"
"vcmpgtsh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpgtuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13904,13910 ****
(match_operand:V4SI 2 "register_operand" "v")] 60))]
"TARGET_ALTIVEC"
"vcmpgtuw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13966,13972 ----
(match_operand:V4SI 2 "register_operand" "v")] 60))]
"TARGET_ALTIVEC"
"vcmpgtuw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpgtsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13912,13918 ****
(match_operand:V4SI 2 "register_operand" "v")] 61))]
"TARGET_ALTIVEC"
"vcmpgtsw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vcmpgtfp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 13974,13980 ----
(match_operand:V4SI 2 "register_operand" "v")] 61))]
"TARGET_ALTIVEC"
"vcmpgtsw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpgtfp"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 13920,13982 ****
(match_operand:V4SF 2 "register_operand" "v")] 62))]
"TARGET_ALTIVEC"
"vcmpgtfp %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 63))]
"TARGET_ALTIVEC"
"vmaxub %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxsb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 64))]
"TARGET_ALTIVEC"
"vmaxsb %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxuh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 65))]
"TARGET_ALTIVEC"
"vmaxuh %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 66))]
"TARGET_ALTIVEC"
"vmaxsh %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 67))]
"TARGET_ALTIVEC"
"vmaxuw %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 68))]
"TARGET_ALTIVEC"
"vmaxsw %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vmaxfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")] 69))]
"TARGET_ALTIVEC"
"vmaxfp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmrghb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 13982,14044 ----
(match_operand:V4SF 2 "register_operand" "v")] 62))]
"TARGET_ALTIVEC"
"vcmpgtfp %0,%1,%2"
! [(set_attr "type" "veccmp")])
! (define_insn "umaxv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxub %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "smaxv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxsb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "umaxv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxuh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "smaxv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxsh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "umaxv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxuw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "smaxv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxsw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "smaxv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vmaxfp %0,%1,%2"
! [(set_attr "type" "veccmp")])
(define_insn "altivec_vmrghb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 13984,13990 ****
(match_operand:V16QI 2 "register_operand" "v")] 70))]
"TARGET_ALTIVEC"
"vmrghb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmrghh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14046,14052 ----
(match_operand:V16QI 2 "register_operand" "v")] 70))]
"TARGET_ALTIVEC"
"vmrghb %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vmrghh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 13992,13998 ****
(match_operand:V8HI 2 "register_operand" "v")] 71))]
"TARGET_ALTIVEC"
"vmrghh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmrghw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14054,14060 ----
(match_operand:V8HI 2 "register_operand" "v")] 71))]
"TARGET_ALTIVEC"
"vmrghh %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vmrghw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14000,14006 ****
(match_operand:V4SI 2 "register_operand" "v")] 72))]
"TARGET_ALTIVEC"
"vmrghw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmrglb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14062,14068 ----
(match_operand:V4SI 2 "register_operand" "v")] 72))]
"TARGET_ALTIVEC"
"vmrghw %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14008,14014 ****
(match_operand:V16QI 2 "register_operand" "v")] 73))]
"TARGET_ALTIVEC"
"vmrglb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmrglh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14070,14076 ----
(match_operand:V16QI 2 "register_operand" "v")] 73))]
"TARGET_ALTIVEC"
"vmrglb %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14016,14022 ****
(match_operand:V8HI 2 "register_operand" "v")] 74))]
"TARGET_ALTIVEC"
"vmrglh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmrglw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14078,14084 ----
(match_operand:V8HI 2 "register_operand" "v")] 74))]
"TARGET_ALTIVEC"
"vmrglh %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vmrglw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14024,14086 ****
(match_operand:V4SI 2 "register_operand" "v")] 75))]
"TARGET_ALTIVEC"
"vmrglw %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminub"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 76))]
"TARGET_ALTIVEC"
"vminub %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminsb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 77))]
"TARGET_ALTIVEC"
"vminsb %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminuh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 78))]
"TARGET_ALTIVEC"
"vminuh %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 79))]
"TARGET_ALTIVEC"
"vminsh %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 80))]
"TARGET_ALTIVEC"
"vminuw %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 81))]
"TARGET_ALTIVEC"
"vminsw %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vminfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")] 82))]
"TARGET_ALTIVEC"
"vminfp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmuleub"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14086,14148 ----
(match_operand:V4SI 2 "register_operand" "v")] 75))]
"TARGET_ALTIVEC"
"vmrglw %0,%1,%2"
! [(set_attr "type" "vecperm")])
! (define_insn "uminv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminub %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "sminv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminsb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "uminv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminuh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "sminv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminsh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "uminv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminuw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "sminv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminsw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "sminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vminfp %0,%1,%2"
! [(set_attr "type" "veccmp")])
(define_insn "altivec_vmuleub"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14088,14094 ****
(match_operand:V16QI 2 "register_operand" "v")] 83))]
"TARGET_ALTIVEC"
"vmuleub %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmulesb"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14150,14156 ----
(match_operand:V16QI 2 "register_operand" "v")] 83))]
"TARGET_ALTIVEC"
"vmuleub %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulesb"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14096,14102 ****
(match_operand:V16QI 2 "register_operand" "v")] 84))]
"TARGET_ALTIVEC"
"vmulesb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmuleuh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14158,14164 ----
(match_operand:V16QI 2 "register_operand" "v")] 84))]
"TARGET_ALTIVEC"
"vmulesb %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmuleuh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14104,14110 ****
(match_operand:V8HI 2 "register_operand" "v")] 85))]
"TARGET_ALTIVEC"
"vmuleuh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmulesh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14166,14172 ----
(match_operand:V8HI 2 "register_operand" "v")] 85))]
"TARGET_ALTIVEC"
"vmuleuh %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulesh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14112,14118 ****
(match_operand:V8HI 2 "register_operand" "v")] 86))]
"TARGET_ALTIVEC"
"vmulesh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmuloub"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14174,14180 ----
(match_operand:V8HI 2 "register_operand" "v")] 86))]
"TARGET_ALTIVEC"
"vmulesh %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmuloub"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14120,14126 ****
(match_operand:V16QI 2 "register_operand" "v")] 87))]
"TARGET_ALTIVEC"
"vmuloub %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmulosb"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14182,14188 ----
(match_operand:V16QI 2 "register_operand" "v")] 87))]
"TARGET_ALTIVEC"
"vmuloub %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulosb"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14128,14134 ****
(match_operand:V16QI 2 "register_operand" "v")] 88))]
"TARGET_ALTIVEC"
"vmulosb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmulouh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14190,14196 ----
(match_operand:V16QI 2 "register_operand" "v")] 88))]
"TARGET_ALTIVEC"
"vmulosb %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulouh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14136,14142 ****
(match_operand:V8HI 2 "register_operand" "v")] 89))]
"TARGET_ALTIVEC"
"vmulouh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vmulosh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14198,14204 ----
(match_operand:V8HI 2 "register_operand" "v")] 89))]
"TARGET_ALTIVEC"
"vmulouh %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vmulosh"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14144,14166 ****
(match_operand:V8HI 2 "register_operand" "v")] 90))]
"TARGET_ALTIVEC"
"vmulosh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vnor"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 91))]
"TARGET_ALTIVEC"
"vnor %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vor"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 92))]
"TARGET_ALTIVEC"
"vor %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhum"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14206,14228 ----
(match_operand:V8HI 2 "register_operand" "v")] 90))]
"TARGET_ALTIVEC"
"vmulosh %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vnor"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v"))))]
"TARGET_ALTIVEC"
"vnor %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "iorv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vor %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vpkuhum"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14168,14174 ****
(match_operand:V8HI 2 "register_operand" "v")] 93))]
"TARGET_ALTIVEC"
"vpkuhum %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwum"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14230,14236 ----
(match_operand:V8HI 2 "register_operand" "v")] 93))]
"TARGET_ALTIVEC"
"vpkuhum %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkuwum"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14176,14182 ****
(match_operand:V4SI 2 "register_operand" "v")] 94))]
"TARGET_ALTIVEC"
"vpkuwum %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkpx"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14238,14244 ----
(match_operand:V4SI 2 "register_operand" "v")] 94))]
"TARGET_ALTIVEC"
"vpkuwum %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkpx"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14184,14190 ****
(match_operand:V4SI 2 "register_operand" "v")] 95))]
"TARGET_ALTIVEC"
"vpkpx %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14246,14252 ----
(match_operand:V4SI 2 "register_operand" "v")] 95))]
"TARGET_ALTIVEC"
"vpkpx %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkuhss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14192,14198 ****
(match_operand:V8HI 2 "register_operand" "v")] 96))]
"TARGET_ALTIVEC"
"vpkuhss %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkshss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14254,14260 ----
(match_operand:V8HI 2 "register_operand" "v")] 96))]
"TARGET_ALTIVEC"
"vpkuhss %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkshss"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14200,14206 ****
(match_operand:V8HI 2 "register_operand" "v")] 97))]
"TARGET_ALTIVEC"
"vpkshss %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14262,14268 ----
(match_operand:V8HI 2 "register_operand" "v")] 97))]
"TARGET_ALTIVEC"
"vpkshss %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkuwss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14208,14214 ****
(match_operand:V4SI 2 "register_operand" "v")] 98))]
"TARGET_ALTIVEC"
"vpkuwss %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkswss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14270,14276 ----
(match_operand:V4SI 2 "register_operand" "v")] 98))]
"TARGET_ALTIVEC"
"vpkuwss %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkswss"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14216,14222 ****
(match_operand:V4SI 2 "register_operand" "v")] 99))]
"TARGET_ALTIVEC"
"vpkswss %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuhus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14278,14284 ----
(match_operand:V4SI 2 "register_operand" "v")] 99))]
"TARGET_ALTIVEC"
"vpkswss %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkuhus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14224,14230 ****
(match_operand:V8HI 2 "register_operand" "v")] 100))]
"TARGET_ALTIVEC"
"vpkuhus %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkshus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14286,14292 ----
(match_operand:V8HI 2 "register_operand" "v")] 100))]
"TARGET_ALTIVEC"
"vpkuhus %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkshus"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14232,14238 ****
(match_operand:V8HI 2 "register_operand" "v")] 101))]
"TARGET_ALTIVEC"
"vpkshus %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkuwus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14294,14300 ----
(match_operand:V8HI 2 "register_operand" "v")] 101))]
"TARGET_ALTIVEC"
"vpkshus %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkuwus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14240,14246 ****
(match_operand:V4SI 2 "register_operand" "v")] 102))]
"TARGET_ALTIVEC"
"vpkuwus %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vpkswus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14302,14308 ----
(match_operand:V4SI 2 "register_operand" "v")] 102))]
"TARGET_ALTIVEC"
"vpkuwus %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vpkswus"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14248,14254 ****
(match_operand:V4SI 2 "register_operand" "v")] 103))]
"TARGET_ALTIVEC"
"vpkswus %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vrlb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14310,14316 ----
(match_operand:V4SI 2 "register_operand" "v")] 103))]
"TARGET_ALTIVEC"
"vpkswus %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vrlb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14256,14262 ****
(match_operand:V16QI 2 "register_operand" "v")] 104))]
"TARGET_ALTIVEC"
"vrlb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vrlh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14318,14324 ----
(match_operand:V16QI 2 "register_operand" "v")] 104))]
"TARGET_ALTIVEC"
"vrlb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vrlh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14264,14270 ****
(match_operand:V8HI 2 "register_operand" "v")] 105))]
"TARGET_ALTIVEC"
"vrlh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vrlw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14326,14332 ----
(match_operand:V8HI 2 "register_operand" "v")] 105))]
"TARGET_ALTIVEC"
"vrlh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vrlw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14272,14278 ****
(match_operand:V4SI 2 "register_operand" "v")] 106))]
"TARGET_ALTIVEC"
"vrlw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vslb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14334,14340 ----
(match_operand:V4SI 2 "register_operand" "v")] 106))]
"TARGET_ALTIVEC"
"vrlw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vslb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14280,14286 ****
(match_operand:V16QI 2 "register_operand" "v")] 107))]
"TARGET_ALTIVEC"
"vslb %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vslh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14342,14348 ----
(match_operand:V16QI 2 "register_operand" "v")] 107))]
"TARGET_ALTIVEC"
"vslb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vslh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14288,14294 ****
(match_operand:V8HI 2 "register_operand" "v")] 108))]
"TARGET_ALTIVEC"
"vslh %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vslw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14350,14356 ----
(match_operand:V8HI 2 "register_operand" "v")] 108))]
"TARGET_ALTIVEC"
"vslh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vslw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14296,14302 ****
(match_operand:V4SI 2 "register_operand" "v")] 109))]
"TARGET_ALTIVEC"
"vslw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14358,14364 ----
(match_operand:V4SI 2 "register_operand" "v")] 109))]
"TARGET_ALTIVEC"
"vslw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14304,14310 ****
(match_operand:V4SI 2 "register_operand" "v")] 110))]
"TARGET_ALTIVEC"
"vsl %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vslo"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14366,14372 ----
(match_operand:V4SI 2 "register_operand" "v")] 110))]
"TARGET_ALTIVEC"
"vsl %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vslo"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14312,14318 ****
(match_operand:V4SI 2 "register_operand" "v")] 111))]
"TARGET_ALTIVEC"
"vslo %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsrb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14374,14380 ----
(match_operand:V4SI 2 "register_operand" "v")] 111))]
"TARGET_ALTIVEC"
"vslo %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vsrb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14320,14342 ****
(match_operand:V16QI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC"
"vsrb %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vrsh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 113))]
"TARGET_ALTIVEC"
! "vrsh %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vrsw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 114))]
"TARGET_ALTIVEC"
! "vrsw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsrab"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14382,14404 ----
(match_operand:V16QI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC"
"vsrb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsrh"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")] 113))]
"TARGET_ALTIVEC"
! "vsrh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsrw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 114))]
"TARGET_ALTIVEC"
! "vsrw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsrab"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14344,14350 ****
(match_operand:V16QI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC"
"vsrab %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsrah"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14406,14412 ----
(match_operand:V16QI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC"
"vsrab %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsrah"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14352,14358 ****
(match_operand:V8HI 2 "register_operand" "v")] 116))]
"TARGET_ALTIVEC"
"vsrah %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsraw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14414,14420 ----
(match_operand:V8HI 2 "register_operand" "v")] 116))]
"TARGET_ALTIVEC"
"vsrah %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsraw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14360,14366 ****
(match_operand:V4SI 2 "register_operand" "v")] 117))]
"TARGET_ALTIVEC"
"vsraw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsr"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14422,14428 ----
(match_operand:V4SI 2 "register_operand" "v")] 117))]
"TARGET_ALTIVEC"
"vsraw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsr"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14368,14374 ****
(match_operand:V4SI 2 "register_operand" "v")] 118))]
"TARGET_ALTIVEC"
"vsr %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsro"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14430,14436 ----
(match_operand:V4SI 2 "register_operand" "v")] 118))]
"TARGET_ALTIVEC"
"vsr %0,%1,%2"
! [(set_attr "type" "vecperm")])
(define_insn "altivec_vsro"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14376,14414 ****
(match_operand:V4SI 2 "register_operand" "v")] 119))]
"TARGET_ALTIVEC"
"vsro %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vsububm"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 120))]
"TARGET_ALTIVEC"
"vsububm %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vsubuhm"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 121))]
"TARGET_ALTIVEC"
"vsubuhm %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vsubuwm"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 122))]
"TARGET_ALTIVEC"
"vsubuwm %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vsubfp"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")] 123))]
"TARGET_ALTIVEC"
"vsubfp %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsubcuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14438,14476 ----
(match_operand:V4SI 2 "register_operand" "v")] 119))]
"TARGET_ALTIVEC"
"vsro %0,%1,%2"
! [(set_attr "type" "vecperm")])
! (define_insn "subv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=v")
! (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vsububm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "subv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=v")
! (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vsubuhm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "subv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vsubuwm %0,%1,%2"
! [(set_attr "type" "vecsimple")])
! (define_insn "subv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=v")
! (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
! (match_operand:V4SF 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vsubfp %0,%1,%2"
! [(set_attr "type" "vecfloat")])
(define_insn "altivec_vsubcuw"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14416,14422 ****
(match_operand:V4SI 2 "register_operand" "v")] 124))]
"TARGET_ALTIVEC"
"vsubcuw %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsububs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14478,14484 ----
(match_operand:V4SI 2 "register_operand" "v")] 124))]
"TARGET_ALTIVEC"
"vsubcuw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsububs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14424,14430 ****
(match_operand:V16QI 2 "register_operand" "v")] 125))]
"TARGET_ALTIVEC"
"vsububs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsubsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
--- 14486,14492 ----
(match_operand:V16QI 2 "register_operand" "v")] 125))]
"TARGET_ALTIVEC"
"vsububs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubsbs"
[(set (match_operand:V16QI 0 "register_operand" "=v")
***************
*** 14432,14438 ****
(match_operand:V16QI 2 "register_operand" "v")] 126))]
"TARGET_ALTIVEC"
"vsubsbs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsubuhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14494,14500 ----
(match_operand:V16QI 2 "register_operand" "v")] 126))]
"TARGET_ALTIVEC"
"vsubsbs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubuhs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14440,14446 ****
(match_operand:V8HI 2 "register_operand" "v")] 127))]
"TARGET_ALTIVEC"
"vsubuhs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsubshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
--- 14502,14508 ----
(match_operand:V8HI 2 "register_operand" "v")] 127))]
"TARGET_ALTIVEC"
"vsubuhs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubshs"
[(set (match_operand:V8HI 0 "register_operand" "=v")
***************
*** 14448,14454 ****
(match_operand:V8HI 2 "register_operand" "v")] 128))]
"TARGET_ALTIVEC"
"vsubshs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsubuws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14510,14516 ----
(match_operand:V8HI 2 "register_operand" "v")] 128))]
"TARGET_ALTIVEC"
"vsubshs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubuws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14456,14462 ****
(match_operand:V4SI 2 "register_operand" "v")] 129))]
"TARGET_ALTIVEC"
"vsubuws %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsubsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14518,14524 ----
(match_operand:V4SI 2 "register_operand" "v")] 129))]
"TARGET_ALTIVEC"
"vsubuws %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsubsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14464,14470 ****
(match_operand:V4SI 2 "register_operand" "v")] 130))]
"TARGET_ALTIVEC"
"vsubsws %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14526,14532 ----
(match_operand:V4SI 2 "register_operand" "v")] 130))]
"TARGET_ALTIVEC"
"vsubsws %0,%1,%2"
! [(set_attr "type" "vecsimple")])
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14472,14478 ****
(match_operand:V4SI 2 "register_operand" "v")] 131))]
"TARGET_ALTIVEC"
"vsum4ubs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsum4sbs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14534,14540 ----
(match_operand:V4SI 2 "register_operand" "v")] 131))]
"TARGET_ALTIVEC"
"vsum4ubs %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vsum4sbs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14480,14486 ****
(match_operand:V4SI 2 "register_operand" "v")] 132))]
"TARGET_ALTIVEC"
"vsum4sbs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsum4shs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14542,14548 ----
(match_operand:V4SI 2 "register_operand" "v")] 132))]
"TARGET_ALTIVEC"
"vsum4sbs %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vsum4shs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14488,14494 ****
(match_operand:V4SI 2 "register_operand" "v")] 133))]
"TARGET_ALTIVEC"
"vsum4shs %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsum2sws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14550,14556 ----
(match_operand:V4SI 2 "register_operand" "v")] 133))]
"TARGET_ALTIVEC"
"vsum4shs %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vsum2sws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14496,14502 ****
(match_operand:V4SI 2 "register_operand" "v")] 134))]
"TARGET_ALTIVEC"
"vsum2sws %0,%1,%2"
! [(set_attr "type" "altivec")])
(define_insn "altivec_vsumsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
--- 14558,14564 ----
(match_operand:V4SI 2 "register_operand" "v")] 134))]
"TARGET_ALTIVEC"
"vsum2sws %0,%1,%2"
! [(set_attr "type" "veccomplex")])
(define_insn "altivec_vsumsws"
[(set (match_operand:V4SI 0 "register_operand" "=v")
***************
*** 14504,14515 ****
(match_operand:V4SI 2 "register_operand" "v")] 135))]
"TARGET_ALTIVEC"
"vsumsws %0,%1,%2"
! [(set_attr "type" "altivec")])
! (define_insn "altivec_vxor"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 136))]
"TARGET_ALTIVEC"
"vxor %0,%1,%2"
! [(set_attr "type" "altivec")])
--- 14566,14577 ----
(match_operand:V4SI 2 "register_operand" "v")] 135))]
"TARGET_ALTIVEC"
"vsumsws %0,%1,%2"
! [(set_attr "type" "veccomplex")])
! (define_insn "xorv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
"vxor %0,%1,%2"
! [(set_attr "type" "vecsimple")])
Index: config/rs6000/sysv4.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/sysv4.h,v
retrieving revision 1.74
diff -c -3 -p -w -B -b -r1.74 sysv4.h
*** sysv4.h 2001/11/22 02:19:56 1.74
--- sysv4.h 2001/11/30 22:23:36
*************** ncrtn.o%s"
*** 1316,1321 ****
--- 1316,1322 ----
%{mcpu=604e: -DCPU=PPC604} \
%{mcpu=620: -DCPU=PPC604} \
%{mcpu=740: -DCPU=PPC603} \
+ %{mcpu=7450: -DCPU=PPC603} \
%{mcpu=750: -DCPU=PPC603} \
%{mcpu=801: -DCPU=PPC603} \
%{mcpu=821: -DCPU=PPC603} \
Index: testsuite/gcc.dg/altivec-1.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/testsuite/gcc.dg/altivec-1.c,v
retrieving revision 1.2
diff -c -3 -p -w -B -b -r1.2 altivec-1.c
*** altivec-1.c 2001/11/20 21:15:52 1.2
--- altivec-1.c 2001/11/30 22:23:36
***************
*** 9,18 ****
overloaded functions implemented in an <altivec.h>. */
#define vec_load(src) \
! __builtin_altivec_ld_internal ((int *) src)
#define vec_store(dst, src) \
! __builtin_altivec_st_internal ((int *) dst, (int4) src)
#define vec_add_int4(x, y) \
__builtin_altivec_vaddsws (x, y)
--- 9,18 ----
overloaded functions implemented in an <altivec.h>. */
#define vec_load(src) \
! __builtin_altivec_ld_internal_4si ((int *) src)
#define vec_store(dst, src) \
! __builtin_altivec_st_internal_4si ((int *) dst, (int4) src)
#define vec_add_int4(x, y) \
__builtin_altivec_vaddsws (x, y)