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Re: altivec.h
- From: Geoff Keating <geoffk at geoffk dot org>
- To: Aldy Hernandez <aldyh at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: 26 Nov 2001 13:20:07 -0800
- Subject: Re: altivec.h
- References: <1006770940.2390.2.camel@litecycle.cc.andrews.edu>
- Reply-to: Geoff Keating <geoffk at redhat dot com>
Aldy Hernandez <aldyh@redhat.com> writes:
> hi folks.
>
> at david's request. i started moving altivec changes to their own
> file.
>
> i'm still waiting for the .md include facility to work so i can move the
> md stuff out, but the .h/.c altivec material also needs to move.
>
> here's a patch to remove the enum and builtin table out of .h/.c and
> into altivec.h. i also changed the names from rs6000_builtin_blah to
> altivec_builtin_blah. bootstrapped on ppc linux gnu.
>
> ok?
>
> ps. what should i do about makefile dependencies? i really don't want
> to add altivec.h to every entry in config.gcc.
Don't worry about it, just do it.
IMO, we should be automatically generating dependencies anyway.
> --
> Aldy Hernandez E-mail: aldyh@redhat.com
> Professional Gypsy
> Red Hat, Inc.
>
> 2001-11-22 Aldy Hernandez <aldyh@redhat.com>
>
> * rs6000.c: Remove bdesc_2arg.
> Include altivec.h.
> (altivec_expand_builtin): Change builtin_description to
> altivec_builtin_description.
> (altivec_init_builtins): Same.
>
> * altivec.h: New file.
>
> * rs6000.h: Remove enum rs6000_builtins.
>
> Index: rs6000.h
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
> retrieving revision 1.141
> diff -c -p -r1.141 rs6000.h
> *** rs6000.h 2001/11/21 01:04:44 1.141
> --- rs6000.h 2001/11/26 10:27:37
> *************** extern int flag_pic;
> *** 2829,2944 ****
> extern int optimize;
> extern int flag_expensive_optimizations;
> extern int frame_pointer_needed;
> -
> - enum rs6000_builtins
> - {
> - /* AltiVec builtins. */
> - ALTIVEC_BUILTIN_ST_INTERNAL,
> - ALTIVEC_BUILTIN_LD_INTERNAL,
> - ALTIVEC_BUILTIN_VADDUBM,
> - ALTIVEC_BUILTIN_VADDUHM,
> - ALTIVEC_BUILTIN_VADDUWM,
> - ALTIVEC_BUILTIN_VADDFP,
> - ALTIVEC_BUILTIN_VADDCUW,
> - ALTIVEC_BUILTIN_VADDUBS,
> - ALTIVEC_BUILTIN_VADDSBS,
> - ALTIVEC_BUILTIN_VADDUHS,
> - ALTIVEC_BUILTIN_VADDSHS,
> - ALTIVEC_BUILTIN_VADDUWS,
> - ALTIVEC_BUILTIN_VADDSWS,
> - ALTIVEC_BUILTIN_VAND,
> - ALTIVEC_BUILTIN_VANDC,
> - ALTIVEC_BUILTIN_VAVGUB,
> - ALTIVEC_BUILTIN_VAVGSB,
> - ALTIVEC_BUILTIN_VAVGUH,
> - ALTIVEC_BUILTIN_VAVGSH,
> - ALTIVEC_BUILTIN_VAVGUW,
> - ALTIVEC_BUILTIN_VAVGSW,
> - ALTIVEC_BUILTIN_VCMPBFP,
> - ALTIVEC_BUILTIN_VCMPEQUB,
> - ALTIVEC_BUILTIN_VCMPEQUH,
> - ALTIVEC_BUILTIN_VCMPEQUW,
> - ALTIVEC_BUILTIN_VCMPEQFP,
> - ALTIVEC_BUILTIN_VCMPGEFP,
> - ALTIVEC_BUILTIN_VCMPGTUB,
> - ALTIVEC_BUILTIN_VCMPGTSB,
> - ALTIVEC_BUILTIN_VCMPGTUH,
> - ALTIVEC_BUILTIN_VCMPGTSH,
> - ALTIVEC_BUILTIN_VCMPGTUW,
> - ALTIVEC_BUILTIN_VCMPGTSW,
> - ALTIVEC_BUILTIN_VCMPGTFP,
> - ALTIVEC_BUILTIN_VMAXUB,
> - ALTIVEC_BUILTIN_VMAXSB,
> - ALTIVEC_BUILTIN_VMAXUH,
> - ALTIVEC_BUILTIN_VMAXSH,
> - ALTIVEC_BUILTIN_VMAXUW,
> - ALTIVEC_BUILTIN_VMAXSW,
> - ALTIVEC_BUILTIN_VMAXFP,
> - ALTIVEC_BUILTIN_VMRGHB,
> - ALTIVEC_BUILTIN_VMRGHH,
> - ALTIVEC_BUILTIN_VMRGHW,
> - ALTIVEC_BUILTIN_VMRGLB,
> - ALTIVEC_BUILTIN_VMRGLH,
> - ALTIVEC_BUILTIN_VMRGLW,
> - ALTIVEC_BUILTIN_VMINUB,
> - ALTIVEC_BUILTIN_VMINSB,
> - ALTIVEC_BUILTIN_VMINUH,
> - ALTIVEC_BUILTIN_VMINSH,
> - ALTIVEC_BUILTIN_VMINUW,
> - ALTIVEC_BUILTIN_VMINSW,
> - ALTIVEC_BUILTIN_VMINFP,
> - ALTIVEC_BUILTIN_VMULEUB,
> - ALTIVEC_BUILTIN_VMULESB,
> - ALTIVEC_BUILTIN_VMULEUH,
> - ALTIVEC_BUILTIN_VMULESH,
> - ALTIVEC_BUILTIN_VMULOUB,
> - ALTIVEC_BUILTIN_VMULOSB,
> - ALTIVEC_BUILTIN_VMULOUH,
> - ALTIVEC_BUILTIN_VMULOSH,
> - ALTIVEC_BUILTIN_VNOR,
> - ALTIVEC_BUILTIN_VOR,
> - ALTIVEC_BUILTIN_VPKUHUM,
> - ALTIVEC_BUILTIN_VPKUWUM,
> - ALTIVEC_BUILTIN_VPKPX,
> - ALTIVEC_BUILTIN_VPKUHSS,
> - ALTIVEC_BUILTIN_VPKSHSS,
> - ALTIVEC_BUILTIN_VPKUWSS,
> - ALTIVEC_BUILTIN_VPKSWSS,
> - ALTIVEC_BUILTIN_VPKUHUS,
> - ALTIVEC_BUILTIN_VPKSHUS,
> - ALTIVEC_BUILTIN_VPKUWUS,
> - ALTIVEC_BUILTIN_VPKSWUS,
> - ALTIVEC_BUILTIN_VRLB,
> - ALTIVEC_BUILTIN_VRLH,
> - ALTIVEC_BUILTIN_VRLW,
> - ALTIVEC_BUILTIN_VSLB,
> - ALTIVEC_BUILTIN_VSLH,
> - ALTIVEC_BUILTIN_VSLW,
> - ALTIVEC_BUILTIN_VSL,
> - ALTIVEC_BUILTIN_VSLO,
> - ALTIVEC_BUILTIN_VSRB,
> - ALTIVEC_BUILTIN_VRSH,
> - ALTIVEC_BUILTIN_VRSW,
> - ALTIVEC_BUILTIN_VSRAB,
> - ALTIVEC_BUILTIN_VSRAH,
> - ALTIVEC_BUILTIN_VSRAW,
> - ALTIVEC_BUILTIN_VSR,
> - ALTIVEC_BUILTIN_VSRO,
> - ALTIVEC_BUILTIN_VSUBUBM,
> - ALTIVEC_BUILTIN_VSUBUHM,
> - ALTIVEC_BUILTIN_VSUBUWM,
> - ALTIVEC_BUILTIN_VSUBFP,
> - ALTIVEC_BUILTIN_VSUBCUW,
> - ALTIVEC_BUILTIN_VSUBUBS,
> - ALTIVEC_BUILTIN_VSUBSBS,
> - ALTIVEC_BUILTIN_VSUBUHS,
> - ALTIVEC_BUILTIN_VSUBSHS,
> - ALTIVEC_BUILTIN_VSUBUWS,
> - ALTIVEC_BUILTIN_VSUBSWS,
> - ALTIVEC_BUILTIN_VSUM4UBS,
> - ALTIVEC_BUILTIN_VSUM4SBS,
> - ALTIVEC_BUILTIN_VSUM4SHS,
> - ALTIVEC_BUILTIN_VSUM2SWS,
> - ALTIVEC_BUILTIN_VSUMSWS,
> - ALTIVEC_BUILTIN_VXOR
> - };
> --- 2829,2831 ----
> Index: rs6000.c
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
> retrieving revision 1.239
> diff -c -p -r1.239 rs6000.c
> *** rs6000.c 2001/11/21 01:04:44 1.239
> --- rs6000.c 2001/11/26 10:28:07
> *************** do { \
> *** 2966,3089 ****
> builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \
> } while (0)
>
> ! struct builtin_description
> ! {
> ! const unsigned int mask;
> ! const enum insn_code icode;
> ! const char *const name;
> ! const enum rs6000_builtins code;
> ! };
> !
> ! /* Simple binary operatiors: VECc = foo (VECa, VECb). */
> ! static const struct builtin_description bdesc_2arg[] =
> ! {
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddubm, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vadduhm, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vadduwm, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddfp, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vand, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxub, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsb, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuh, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsh, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuw, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsw, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmaxfp, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminub, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminsb, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminuh, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminsh, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminuw, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminsw, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vminfp, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vor, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vrsh, "__builtin_altivec_vrsh", ALTIVEC_BUILTIN_VRSH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vrsw, "__builtin_altivec_vrsw", ALTIVEC_BUILTIN_VRSW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsububm, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhm, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubuwm, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubfp, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
> ! { MASK_ALTIVEC, CODE_FOR_altivec_vxor, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
> ! };
>
> static rtx
> altivec_expand_binop_builtin (icode, arglist, target)
> --- 2966,2972 ----
> builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \
> } while (0)
>
> ! #include "altivec.h"
>
> static rtx
> altivec_expand_binop_builtin (icode, arglist, target)
> *************** altivec_expand_builtin (exp, target)
> *** 3123,3129 ****
> tree exp;
> rtx target;
> {
> ! struct builtin_description *d;
> size_t i;
> enum insn_code icode;
> tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
> --- 3006,3012 ----
> tree exp;
> rtx target;
> {
> ! struct altivec_builtin_description *d;
> size_t i;
> enum insn_code icode;
> tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
> *************** altivec_expand_builtin (exp, target)
> *** 3178,3184 ****
> }
>
> /* Handle simple binary operations. */
> ! d = (struct builtin_description *) bdesc_2arg;
> for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
> if (d->code == fcode)
> return altivec_expand_binop_builtin (d->icode, arglist, target);
> --- 3061,3067 ----
> }
>
> /* Handle simple binary operations. */
> ! d = (struct altivec_builtin_description *) bdesc_2arg;
> for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
> if (d->code == fcode)
> return altivec_expand_binop_builtin (d->icode, arglist, target);
> *************** rs6000_init_builtins (list_node)
> *** 3218,3224 ****
> static void
> altivec_init_builtins (void)
> {
> ! struct builtin_description * d;
> size_t i;
>
> tree endlink = void_list_node;
> --- 3101,3107 ----
> static void
> altivec_init_builtins (void)
> {
> ! struct altivec_builtin_description * d;
> size_t i;
>
> tree endlink = void_list_node;
> *************** altivec_init_builtins (void)
> *** 3331,3337 ****
> def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL);
>
> /* Add the simple binary operators. */
> ! d = (struct builtin_description *) bdesc_2arg;
> for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
> {
> enum machine_mode mode0, mode1, mode2;
> --- 3214,3220 ----
> def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL);
>
> /* Add the simple binary operators. */
> ! d = (struct altivec_builtin_description *) bdesc_2arg;
> for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
> {
> enum machine_mode mode0, mode1, mode2;
> Index: altivec.h
> ===================================================================
> RCS file: altivec.h
> diff -N altivec.h
> *** /dev/null Tue May 5 13:32:27 1998
> --- altivec.h Mon Nov 26 02:28:07 2001
> ***************
> *** 0 ****
> --- 1,252 ----
> + /* AltiVec builtins.
> + Copyright (C) 2001 Free Software Foundation, Inc.
> + Contributed by Aldy Hernandez (aldyh@redhat.com).
> +
> + This file is part of GNU CC.
> +
> + GNU CC is free software; you can redistribute it and/or modify
> + it under the terms of the GNU General Public License as published by
> + the Free Software Foundation; either version 2, or (at your option)
> + any later version.
> +
> + GNU CC is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + GNU General Public License for more details.
> +
> + You should have received a copy of the GNU General Public License
> + along with GNU CC; see the file COPYING. If not, write to
> + the Free Software Foundation, 59 Temple Place - Suite 330,
> + Boston, MA 02111-1307, USA. */
> +
> + enum altivec_builtins
> + {
> + /* AltiVec builtins. */
> + ALTIVEC_BUILTIN_ST_INTERNAL,
> + ALTIVEC_BUILTIN_LD_INTERNAL,
> + ALTIVEC_BUILTIN_VADDUBM,
> + ALTIVEC_BUILTIN_VADDUHM,
> + ALTIVEC_BUILTIN_VADDUWM,
> + ALTIVEC_BUILTIN_VADDFP,
> + ALTIVEC_BUILTIN_VADDCUW,
> + ALTIVEC_BUILTIN_VADDUBS,
> + ALTIVEC_BUILTIN_VADDSBS,
> + ALTIVEC_BUILTIN_VADDUHS,
> + ALTIVEC_BUILTIN_VADDSHS,
> + ALTIVEC_BUILTIN_VADDUWS,
> + ALTIVEC_BUILTIN_VADDSWS,
> + ALTIVEC_BUILTIN_VAND,
> + ALTIVEC_BUILTIN_VANDC,
> + ALTIVEC_BUILTIN_VAVGUB,
> + ALTIVEC_BUILTIN_VAVGSB,
> + ALTIVEC_BUILTIN_VAVGUH,
> + ALTIVEC_BUILTIN_VAVGSH,
> + ALTIVEC_BUILTIN_VAVGUW,
> + ALTIVEC_BUILTIN_VAVGSW,
> + ALTIVEC_BUILTIN_VCMPBFP,
> + ALTIVEC_BUILTIN_VCMPEQUB,
> + ALTIVEC_BUILTIN_VCMPEQUH,
> + ALTIVEC_BUILTIN_VCMPEQUW,
> + ALTIVEC_BUILTIN_VCMPEQFP,
> + ALTIVEC_BUILTIN_VCMPGEFP,
> + ALTIVEC_BUILTIN_VCMPGTUB,
> + ALTIVEC_BUILTIN_VCMPGTSB,
> + ALTIVEC_BUILTIN_VCMPGTUH,
> + ALTIVEC_BUILTIN_VCMPGTSH,
> + ALTIVEC_BUILTIN_VCMPGTUW,
> + ALTIVEC_BUILTIN_VCMPGTSW,
> + ALTIVEC_BUILTIN_VCMPGTFP,
> + ALTIVEC_BUILTIN_VMAXUB,
> + ALTIVEC_BUILTIN_VMAXSB,
> + ALTIVEC_BUILTIN_VMAXUH,
> + ALTIVEC_BUILTIN_VMAXSH,
> + ALTIVEC_BUILTIN_VMAXUW,
> + ALTIVEC_BUILTIN_VMAXSW,
> + ALTIVEC_BUILTIN_VMAXFP,
> + ALTIVEC_BUILTIN_VMRGHB,
> + ALTIVEC_BUILTIN_VMRGHH,
> + ALTIVEC_BUILTIN_VMRGHW,
> + ALTIVEC_BUILTIN_VMRGLB,
> + ALTIVEC_BUILTIN_VMRGLH,
> + ALTIVEC_BUILTIN_VMRGLW,
> + ALTIVEC_BUILTIN_VMINUB,
> + ALTIVEC_BUILTIN_VMINSB,
> + ALTIVEC_BUILTIN_VMINUH,
> + ALTIVEC_BUILTIN_VMINSH,
> + ALTIVEC_BUILTIN_VMINUW,
> + ALTIVEC_BUILTIN_VMINSW,
> + ALTIVEC_BUILTIN_VMINFP,
> + ALTIVEC_BUILTIN_VMULEUB,
> + ALTIVEC_BUILTIN_VMULESB,
> + ALTIVEC_BUILTIN_VMULEUH,
> + ALTIVEC_BUILTIN_VMULESH,
> + ALTIVEC_BUILTIN_VMULOUB,
> + ALTIVEC_BUILTIN_VMULOSB,
> + ALTIVEC_BUILTIN_VMULOUH,
> + ALTIVEC_BUILTIN_VMULOSH,
> + ALTIVEC_BUILTIN_VNOR,
> + ALTIVEC_BUILTIN_VOR,
> + ALTIVEC_BUILTIN_VPKUHUM,
> + ALTIVEC_BUILTIN_VPKUWUM,
> + ALTIVEC_BUILTIN_VPKPX,
> + ALTIVEC_BUILTIN_VPKUHSS,
> + ALTIVEC_BUILTIN_VPKSHSS,
> + ALTIVEC_BUILTIN_VPKUWSS,
> + ALTIVEC_BUILTIN_VPKSWSS,
> + ALTIVEC_BUILTIN_VPKUHUS,
> + ALTIVEC_BUILTIN_VPKSHUS,
> + ALTIVEC_BUILTIN_VPKUWUS,
> + ALTIVEC_BUILTIN_VPKSWUS,
> + ALTIVEC_BUILTIN_VRLB,
> + ALTIVEC_BUILTIN_VRLH,
> + ALTIVEC_BUILTIN_VRLW,
> + ALTIVEC_BUILTIN_VSLB,
> + ALTIVEC_BUILTIN_VSLH,
> + ALTIVEC_BUILTIN_VSLW,
> + ALTIVEC_BUILTIN_VSL,
> + ALTIVEC_BUILTIN_VSLO,
> + ALTIVEC_BUILTIN_VSRB,
> + ALTIVEC_BUILTIN_VRSH,
> + ALTIVEC_BUILTIN_VRSW,
> + ALTIVEC_BUILTIN_VSRAB,
> + ALTIVEC_BUILTIN_VSRAH,
> + ALTIVEC_BUILTIN_VSRAW,
> + ALTIVEC_BUILTIN_VSR,
> + ALTIVEC_BUILTIN_VSRO,
> + ALTIVEC_BUILTIN_VSUBUBM,
> + ALTIVEC_BUILTIN_VSUBUHM,
> + ALTIVEC_BUILTIN_VSUBUWM,
> + ALTIVEC_BUILTIN_VSUBFP,
> + ALTIVEC_BUILTIN_VSUBCUW,
> + ALTIVEC_BUILTIN_VSUBUBS,
> + ALTIVEC_BUILTIN_VSUBSBS,
> + ALTIVEC_BUILTIN_VSUBUHS,
> + ALTIVEC_BUILTIN_VSUBSHS,
> + ALTIVEC_BUILTIN_VSUBUWS,
> + ALTIVEC_BUILTIN_VSUBSWS,
> + ALTIVEC_BUILTIN_VSUM4UBS,
> + ALTIVEC_BUILTIN_VSUM4SBS,
> + ALTIVEC_BUILTIN_VSUM4SHS,
> + ALTIVEC_BUILTIN_VSUM2SWS,
> + ALTIVEC_BUILTIN_VSUMSWS,
> + ALTIVEC_BUILTIN_VXOR
> + };
> +
> + struct altivec_builtin_description
> + {
> + const unsigned int mask;
> + const enum insn_code icode;
> + const char *const name;
> + const enum altivec_builtins code;
> + };
> +
> + /* Simple binary operatiors: VECc = foo (VECa, VECb). */
> + static const struct altivec_builtin_description bdesc_2arg[] =
> + {
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddubm, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vadduhm, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vadduwm, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddfp, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vand, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxub, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsb, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuh, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsh, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxuw, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxsw, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmaxfp, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminub, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminsb, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminuh, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminsh, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminuw, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminsw, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vminfp, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vor, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vrsh, "__builtin_altivec_vrsh", ALTIVEC_BUILTIN_VRSH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vrsw, "__builtin_altivec_vrsw", ALTIVEC_BUILTIN_VRSW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsububm, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhm, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubuwm, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubfp, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
> + { MASK_ALTIVEC, CODE_FOR_altivec_vxor, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
> + };
--
- Geoffrey Keating <geoffk@geoffk.org> <geoffk@redhat.com>