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sparc cleanup



Hi,
the sparc backend contains many calls to alter_subreg that are dead now,
as we avoid the subregs after reload.

Bootstrapped/regtested sparc.

Thu Nov 22 14:45:29 CET 2001  Jan Hubicka  <jh@suse.cz>
	* sparc.c (sparc_absnegfloat_split_legitimate): Do not call
	alter_subreg.
	* sparc.md (post-reload splitters): Do not call alter_subreg.

Index: config/sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.c,v
retrieving revision 1.163
diff -c -3 -p -r1.163 sparc.c
*** sparc.c	2001/11/16 11:33:23	1.163
--- sparc.c	2001/11/22 13:33:26
*************** int
*** 5605,5616 ****
  sparc_absnegfloat_split_legitimate (x, y)
       rtx x, y;
  {
-   if (GET_CODE (x) == SUBREG)
-     x = alter_subreg (x);
    if (GET_CODE (x) != REG)
      return 0;
-   if (GET_CODE (y) == SUBREG)
-     y = alter_subreg (y);
    if (GET_CODE (y) != REG)
      return 0;
    if (REGNO (x) == REGNO (y))
--- 5605,5612 ----
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.135
diff -c -3 -p -r1.135 sparc.md
*** sparc.md	2001/11/09 14:30:33	1.135
--- sparc.md	2001/11/22 13:33:29
***************
*** 2798,2808 ****
    rtx dest1, dest2;
    rtx src1, src2;
  
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
-   if (GET_CODE (set_src) == SUBREG)
-     set_src = alter_subreg (set_src);
- 
    dest1 = gen_highpart (SImode, set_dest);
    dest2 = gen_lowpart (SImode, set_dest);
    src1 = gen_highpart (SImode, set_src);
--- 2798,2803 ----
***************
*** 3366,3373 ****
  
    REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
    REAL_VALUE_TO_TARGET_DOUBLE (r, l);
-   if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
    operands[0] = gen_rtx_raw_REG (DImode, REGNO (operands[0]));
  
    if (TARGET_ARCH64)
--- 3361,3366 ----
***************
*** 3430,3440 ****
    rtx dest1, dest2;
    rtx src1, src2;
  
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
-   if (GET_CODE (set_src) == SUBREG)
-     set_src = alter_subreg (set_src);
- 
    dest1 = gen_highpart (SFmode, set_dest);
    dest2 = gen_lowpart (SFmode, set_dest);
    src1 = gen_highpart (SFmode, set_src);
--- 3423,3428 ----
***************
*** 3469,3477 ****
    rtx word0 = adjust_address (operands[1], SFmode, 0);
    rtx word1 = adjust_address (operands[1], SFmode, 4);
  
-   if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
- 
    if (reg_overlap_mentioned_p (gen_highpart (SFmode, operands[0]), word1))
      {
        emit_insn (gen_movsf (gen_lowpart (SFmode, operands[0]),
--- 3457,3462 ----
***************
*** 3503,3510 ****
    rtx word0 = adjust_address (operands[0], SFmode, 0);
    rtx word1 = adjust_address (operands[0], SFmode, 4);
  
-   if (GET_CODE (operands[1]) == SUBREG)
-     operands[1] = alter_subreg (operands[1]);
    emit_insn (gen_movsf (word0,
  			gen_highpart (SFmode, operands[1])));
    emit_insn (gen_movsf (word1,
--- 3488,3493 ----
***************
*** 3549,3556 ****
    rtx set_dest = operands[0];
    rtx dest1, dest2;
  
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
    dest1 = gen_highpart (SFmode, set_dest);
    dest2 = gen_lowpart (SFmode, set_dest);
    emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode)));
--- 3532,3537 ----
***************
*** 3754,3764 ****
    rtx dest1, dest2;
    rtx src1, src2;
  
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
-   if (GET_CODE (set_src) == SUBREG)
-     set_src = alter_subreg (set_src);
- 
    dest1 = gen_df_reg (set_dest, 0);
    dest2 = gen_df_reg (set_dest, 1);
    src1 = gen_df_reg (set_src, 0);
--- 3735,3740 ----
***************
*** 3791,3799 ****
  
    switch (GET_CODE (set_dest))
      {
-     case SUBREG:
-       set_dest = alter_subreg (set_dest);
-       /* FALLTHROUGH */
      case REG:
        dest1 = gen_df_reg (set_dest, 0);
        dest2 = gen_df_reg (set_dest, 1);
--- 3767,3772 ----
***************
*** 3824,3831 ****
    rtx set_dest, dest1, dest2;
  
    set_dest = operands[0];
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
  
    dest1 = gen_df_reg (set_dest, 0);
    dest2 = gen_df_reg (set_dest, 1);
--- 3797,3802 ----
***************
*** 3855,3862 ****
    "
  {
    rtx set_src = operands[1];
-   if (GET_CODE (set_src) == SUBREG)
-     set_src = alter_subreg (set_src);
  
    emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
  			gen_df_reg (set_src, 0)));
--- 3826,3831 ----
***************
*** 4214,4226 ****
    rtx dest1, dest2;
    rtx srca1, srca2, srcb1, srcb2;
  
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
-   if (GET_CODE (set_srca) == SUBREG)
-     set_srca = alter_subreg (set_srca);
-   if (GET_CODE (set_srcb) == SUBREG)
-     set_srcb = alter_subreg (set_srcb);
- 
    dest1 = gen_df_reg (set_dest, 0);
    dest2 = gen_df_reg (set_dest, 1);
    srca1 = gen_df_reg (set_srca, 0);
--- 4183,4188 ----
***************
*** 4379,4391 ****
    rtx dest1, dest2;
    rtx srca1, srca2, srcb1, srcb2;
  
-   if (GET_CODE (set_dest) == SUBREG)
-     set_dest = alter_subreg (set_dest);
-   if (GET_CODE (set_srca) == SUBREG)
-     set_srca = alter_subreg (set_srca);
-   if (GET_CODE (set_srcb) == SUBREG)
-     set_srcb = alter_subreg (set_srcb);
- 
    dest1 = gen_df_reg (set_dest, 0);
    dest2 = gen_df_reg (set_dest, 1);
    srca1 = gen_df_reg (set_srca, 0);
--- 4341,4346 ----
***************
*** 4558,4566 ****
  {
    rtx dest1, dest2;
  
-   if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
- 
    dest1 = gen_highpart (SImode, operands[0]);
    dest2 = gen_lowpart (SImode, operands[0]);
  
--- 4513,4518 ----
***************
*** 6617,6624 ****
     (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))]
    "
  {
-   if (GET_CODE (operands[0]) == SUBREG)
-     operands[0] = alter_subreg (operands[0]);
    operands[4] = gen_highpart (SImode, operands[0]);
    operands[5] = gen_lowpart (SImode, operands[0]);
    operands[6] = gen_highpart (SImode, operands[2]);
--- 6569,6574 ----
***************
*** 6662,6670 ****
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
     (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    operands[3] = gen_highpart (SImode, operands[0]);
     operands[4] = gen_highpart (SImode, operands[1]);
     operands[5] = gen_highpart (SImode, operands[2]);
     operands[6] = gen_lowpart (SImode, operands[0]);
--- 6612,6618 ----
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))
     (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))]
!   "operands[3] = gen_highpart (SImode, operands[0]);
     operands[4] = gen_highpart (SImode, operands[1]);
     operands[5] = gen_highpart (SImode, operands[2]);
     operands[6] = gen_lowpart (SImode, operands[0]);
***************
*** 6772,6780 ****
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
     (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    operands[3] = gen_highpart (SImode, operands[0]);
     operands[4] = gen_highpart (SImode, operands[1]);
     operands[5] = gen_highpart (SImode, operands[2]);
     operands[6] = gen_lowpart (SImode, operands[0]);
--- 6720,6726 ----
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))
     (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))]
!   "operands[3] = gen_highpart (SImode, operands[0]);
     operands[4] = gen_highpart (SImode, operands[1]);
     operands[5] = gen_highpart (SImode, operands[2]);
     operands[6] = gen_lowpart (SImode, operands[0]);
***************
*** 6907,6915 ****
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
     (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    operands[3] = gen_highpart (SImode, operands[0]);
     operands[4] = gen_highpart (SImode, operands[1]);
     operands[5] = gen_highpart (SImode, operands[2]);
     operands[6] = gen_lowpart (SImode, operands[0]);
--- 6853,6859 ----
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5))))
     (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))]
!   "operands[3] = gen_highpart (SImode, operands[0]);
     operands[4] = gen_highpart (SImode, operands[1]);
     operands[5] = gen_highpart (SImode, operands[2]);
     operands[6] = gen_lowpart (SImode, operands[0]);
***************
*** 7209,7217 ****
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
     (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    operands[2] = gen_highpart (SImode, operands[0]);
     operands[3] = gen_highpart (SImode, operands[1]);
     operands[4] = gen_lowpart (SImode, operands[0]);
     operands[5] = gen_lowpart (SImode, operands[1]);")
--- 7153,7159 ----
             && REGNO (SUBREG_REG (operands[0])) < 32))"
    [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0))))
     (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))]
!   "operands[2] = gen_highpart (SImode, operands[0]);
     operands[3] = gen_highpart (SImode, operands[1]);
     operands[4] = gen_lowpart (SImode, operands[0]);
     operands[5] = gen_lowpart (SImode, operands[1]);")
***************
*** 7587,7597 ****
    [(set (match_dup 2) (neg:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))
     (set (match_dup 6) (match_dup 7))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    if (GET_CODE (operands[1]) == SUBREG)
!      operands[1] = alter_subreg (operands[1]);
!    operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
--- 7529,7535 ----
    [(set (match_dup 2) (neg:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))
     (set (match_dup 6) (match_dup 7))]
!   "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
***************
*** 7619,7629 ****
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (neg:DF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    if (GET_CODE (operands[1]) == SUBREG)
!      operands[1] = alter_subreg (operands[1]);
!    operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
     operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
--- 7557,7563 ----
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (neg:DF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
     operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
***************
*** 7653,7663 ****
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (neg:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    if (GET_CODE (operands[1]) == SUBREG)
!      operands[1] = alter_subreg (operands[1]);
!    operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
--- 7587,7593 ----
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (neg:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
***************
*** 7704,7714 ****
    [(set (match_dup 2) (abs:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))
     (set (match_dup 6) (match_dup 7))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    if (GET_CODE (operands[1]) == SUBREG)
!      operands[1] = alter_subreg (operands[1]);
!    operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
--- 7634,7640 ----
    [(set (match_dup 2) (abs:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))
     (set (match_dup 6) (match_dup 7))]
!   "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);
***************
*** 7745,7755 ****
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (abs:DF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    if (GET_CODE (operands[1]) == SUBREG)
!      operands[1] = alter_subreg (operands[1]);
!    operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
     operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
--- 7671,7677 ----
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (abs:DF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2);
     operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);")
***************
*** 7779,7789 ****
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (abs:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "if (GET_CODE (operands[0]) == SUBREG)
!      operands[0] = alter_subreg (operands[0]);
!    if (GET_CODE (operands[1]) == SUBREG)
!      operands[1] = alter_subreg (operands[1]);
!    operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")
--- 7701,7707 ----
     && sparc_absnegfloat_split_legitimate (operands[0], operands[1])"
    [(set (match_dup 2) (abs:SF (match_dup 3)))
     (set (match_dup 4) (match_dup 5))]
!   "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]));
     operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]));
     operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1);
     operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);")


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