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alpha divide cleanup
- To: gcc-patches at gcc dot gnu dot org
- Subject: alpha divide cleanup
- From: Richard Henderson <rth at redhat dot com>
- Date: Fri, 26 Oct 2001 01:07:27 -0700
While testing Steve Christiansen's loop patch on Alpha, I discovered
that loop will do some copy-propagation without verifying that the
replacement is valid.
This is a bug, for sure, but I figure that if I tried to fix loop,
I'd still be at it. Instead, I rearranged the Alpha divide patterns
to avoid the use of non-fixed hard registers. Which is almost certainly
better for the optimizers anyway.
Tested with a C only bootstrap on alphaev6-linux; I run afoul of Jan's
cfg changes once I get past that.
r~
* config/alpha/alpha.h (enum reg_class): Add R24_REG, R25_REG;
rename PV_REG to R27_REG.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
(REG_CLASS_FROM_LETTER): Update.
(PREFERRED_RELOAD_CLASS): Don't widen a reg class.
* config/alpha/alpha.md (divsi3): Don't hard-code r24, r25, r27.
(udivsi3, modsi3, umodsi3): Likewise.
(divdi3, udivdi3, moddi3, umoddi3): Likewise.
Index: alpha.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.h,v
retrieving revision 1.138
diff -c -p -d -r1.138 alpha.h
*** alpha.h 2001/10/21 21:32:12 1.138
--- alpha.h 2001/10/26 07:53:03
*************** extern const char *alpha_mlat_string; /*
*** 729,750 ****
For any two classes, it is very desirable that there be another
class that represents their union. */
! enum reg_class { NO_REGS, PV_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
! LIM_REG_CLASSES };
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
! {"NO_REGS", "PV_REG", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
! #define REG_CLASS_CONTENTS \
! { {0, 0}, {0x08000000, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
/* The same information, inverted:
Return the class number of the smallest class containing
--- 729,760 ----
For any two classes, it is very desirable that there be another
class that represents their union. */
! enum reg_class {
! NO_REGS, R24_REG, R25_REG, R27_REG,
! GENERAL_REGS, FLOAT_REGS, ALL_REGS,
! LIM_REG_CLASSES
! };
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
! {"NO_REGS", "R24_REG", "R25_REG", "R27_REG", \
! "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
! #define REG_CLASS_CONTENTS \
! { {0x00000000, 0x00000000}, /* NO_REGS */ \
! {0x01000000, 0x00000000}, /* R24_REG */ \
! {0x02000000, 0x00000000}, /* R25_REG */ \
! {0x08000000, 0x00000000}, /* R27_REG */ \
! {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \
! {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \
! {0xffffffff, 0xffffffff} }
/* The same information, inverted:
Return the class number of the smallest class containing
*************** enum reg_class { NO_REGS, PV_REG, GENERA
*** 752,758 ****
or could index an array. */
#define REGNO_REG_CLASS(REGNO) \
! ((REGNO) == 27 ? PV_REG \
: (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
: GENERAL_REGS)
--- 762,770 ----
or could index an array. */
#define REGNO_REG_CLASS(REGNO) \
! ((REGNO) == 24 ? R24_REG \
! : (REGNO) == 25 ? R25_REG \
! : (REGNO) == 27 ? R27_REG \
: (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
: GENERAL_REGS)
*************** enum reg_class { NO_REGS, PV_REG, GENERA
*** 763,769 ****
/* Get reg_class from a letter such as appears in the machine description. */
#define REG_CLASS_FROM_LETTER(C) \
! ((C) == 'c' ? PV_REG : (C) == 'f' ? FLOAT_REGS : NO_REGS)
/* Define this macro to change register usage conditional on target flags. */
/* #define CONDITIONAL_REGISTER_USAGE */
--- 775,785 ----
/* Get reg_class from a letter such as appears in the machine description. */
#define REG_CLASS_FROM_LETTER(C) \
! ((C) == 'a' ? R24_REG \
! : (C) == 'b' ? R25_REG \
! : (C) == 'c' ? R27_REG \
! : (C) == 'f' ? FLOAT_REGS \
! : NO_REGS)
/* Define this macro to change register usage conditional on target flags. */
/* #define CONDITIONAL_REGISTER_USAGE */
*************** enum reg_class { NO_REGS, PV_REG, GENERA
*** 840,848 ****
On the Alpha, all constants except zero go into a floating-point
register via memory. */
! #define PREFERRED_RELOAD_CLASS(X, CLASS) \
! (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
! ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS) \
: (CLASS))
/* Loading and storing HImode or QImode values to and from memory
--- 856,865 ----
On the Alpha, all constants except zero go into a floating-point
register via memory. */
! #define PREFERRED_RELOAD_CLASS(X, CLASS) \
! (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
! ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS \
! : (CLASS) == ALL_REGS ? GENERAL_REGS : (CLASS)) \
: (CLASS))
/* Loading and storing HImode or QImode values to and from memory
Index: alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.155
diff -c -p -d -r1.155 alpha.md
*** alpha.md 2001/10/19 05:04:54 1.155
--- alpha.md 2001/10/26 07:53:04
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1019,1109 ****
;; extension?
(define_expand "divsi3"
! [(set (reg:DI 24)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (reg:DI 25)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (reg:DI 27) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "")
(define_expand "udivsi3"
! [(set (reg:DI 24)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (reg:DI 25)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (reg:DI 27) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "")
(define_expand "modsi3"
! [(set (reg:DI 24)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (reg:DI 25)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (reg:DI 27) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "")
(define_expand "umodsi3"
! [(set (reg:DI 24)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (reg:DI 25)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (reg:DI 27) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "")
(define_expand "divdi3"
! [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
! (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
! (parallel [(set (reg:DI 27)
! (div:DI (reg:DI 24)
! (reg:DI 25)))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:DI 0 "nonimmediate_operand" "")
! (reg:DI 27))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
(define_expand "udivdi3"
! [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
! (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
! (parallel [(set (reg:DI 27)
! (udiv:DI (reg:DI 24)
! (reg:DI 25)))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:DI 0 "nonimmediate_operand" "")
! (reg:DI 27))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
(define_expand "moddi3"
! [(use (match_operand:DI 0 "nonimmediate_operand" ""))
! (use (match_operand:DI 1 "input_operand" ""))
! (use (match_operand:DI 2 "input_operand" ""))]
"!TARGET_ABI_OPEN_VMS"
{
if (TARGET_ABI_UNICOSMK)
--- 1019,1117 ----
;; extension?
(define_expand "divsi3"
! [(set (match_dup 3)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (match_dup 4)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (match_dup 5)
! (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (match_dup 5) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! {
! operands[3] = gen_reg_rtx (DImode);
! operands[4] = gen_reg_rtx (DImode);
! operands[5] = gen_reg_rtx (DImode);
! })
(define_expand "udivsi3"
! [(set (match_dup 3)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (match_dup 4)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (match_dup 5)
! (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (match_dup 5) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! {
! operands[3] = gen_reg_rtx (DImode);
! operands[4] = gen_reg_rtx (DImode);
! operands[5] = gen_reg_rtx (DImode);
! })
(define_expand "modsi3"
! [(set (match_dup 3)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (match_dup 4)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (match_dup 5)
! (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (match_dup 5) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! {
! operands[3] = gen_reg_rtx (DImode);
! operands[4] = gen_reg_rtx (DImode);
! operands[5] = gen_reg_rtx (DImode);
! })
(define_expand "umodsi3"
! [(set (match_dup 3)
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
! (set (match_dup 4)
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
! (parallel [(set (match_dup 5)
! (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
(set (match_operand:SI 0 "nonimmediate_operand" "")
! (subreg:SI (match_dup 5) 0))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! {
! operands[3] = gen_reg_rtx (DImode);
! operands[4] = gen_reg_rtx (DImode);
! operands[5] = gen_reg_rtx (DImode);
! })
(define_expand "divdi3"
! [(parallel [(set (match_operand:DI 0 "register_operand" "")
! (div:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:DI 2 "register_operand" "")))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
(define_expand "udivdi3"
! [(parallel [(set (match_operand:DI 0 "register_operand" "")
! (udiv:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:DI 2 "register_operand" "")))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
(define_expand "moddi3"
! [(use (match_operand:DI 0 "register_operand" ""))
! (use (match_operand:DI 1 "register_operand" ""))
! (use (match_operand:DI 2 "register_operand" ""))]
"!TARGET_ABI_OPEN_VMS"
{
if (TARGET_ABI_UNICOSMK)
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1114,1128 ****
})
(define_expand "moddi3_dft"
! [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
! (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
! (parallel [(set (reg:DI 27)
! (mod:DI (reg:DI 24)
! (reg:DI 25)))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:DI 0 "nonimmediate_operand" "")
! (reg:DI 27))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
--- 1122,1132 ----
})
(define_expand "moddi3_dft"
! [(parallel [(set (match_operand:DI 0 "register_operand" "")
! (mod:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:DI 2 "register_operand" "")))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1130,1160 ****
;; compute the quotient, multiply and subtract.
(define_expand "moddi3_umk"
! [(use (match_operand:DI 0 "nonimmediate_operand" ""))
! (use (match_operand:DI 1 "input_operand" ""))
! (use (match_operand:DI 2 "input_operand" ""))]
"TARGET_ABI_UNICOSMK"
{
! rtx mul, div, tmp;
!
! mul = gen_reg_rtx (DImode);
! tmp = gen_reg_rtx (DImode);
! operands[1] = force_reg (DImode, operands[1]);
! operands[2] = force_reg (DImode, operands[2]);
div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
NULL_RTX, 0, OPTAB_LIB);
div = force_reg (DImode, div);
emit_insn (gen_muldi3 (mul, operands[2], div));
! emit_insn (gen_subdi3 (tmp, operands[1], mul));
! emit_move_insn (operands[0], tmp);
DONE;
})
(define_expand "umoddi3"
! [(use (match_operand:DI 0 "nonimmediate_operand" ""))
! (use (match_operand:DI 1 "input_operand" ""))
! (use (match_operand:DI 2 "input_operand" ""))]
"! TARGET_ABI_OPEN_VMS"
{
if (TARGET_ABI_UNICOSMK)
--- 1134,1158 ----
;; compute the quotient, multiply and subtract.
(define_expand "moddi3_umk"
! [(use (match_operand:DI 0 "register_operand" ""))
! (use (match_operand:DI 1 "register_operand" ""))
! (use (match_operand:DI 2 "register_operand" ""))]
"TARGET_ABI_UNICOSMK"
{
! rtx div, mul = gen_reg_rtx (DImode);
div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
NULL_RTX, 0, OPTAB_LIB);
div = force_reg (DImode, div);
emit_insn (gen_muldi3 (mul, operands[2], div));
! emit_insn (gen_subdi3 (operands[0], operands[1], mul));
DONE;
})
(define_expand "umoddi3"
! [(use (match_operand:DI 0 "register_operand" ""))
! (use (match_operand:DI 1 "register_operand" ""))
! (use (match_operand:DI 2 "register_operand" ""))]
"! TARGET_ABI_OPEN_VMS"
{
if (TARGET_ABI_UNICOSMK)
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1165,1201 ****
})
(define_expand "umoddi3_dft"
! [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
! (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
! (parallel [(set (reg:DI 27)
! (umod:DI (reg:DI 24)
! (reg:DI 25)))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:DI 0 "nonimmediate_operand" "")
! (reg:DI 27))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
(define_expand "umoddi3_umk"
! [(use (match_operand:DI 0 "nonimmediate_operand" ""))
! (use (match_operand:DI 1 "input_operand" ""))
! (use (match_operand:DI 2 "input_operand" ""))]
"TARGET_ABI_UNICOSMK"
{
! rtx mul, div, tmp;
!
! mul = gen_reg_rtx (DImode);
! tmp = gen_reg_rtx (DImode);
! operands[1] = force_reg (DImode, operands[1]);
! operands[2] = force_reg (DImode, operands[2]);
div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
NULL_RTX, 1, OPTAB_LIB);
div = force_reg (DImode, div);
emit_insn (gen_muldi3 (mul, operands[2], div));
! emit_insn (gen_subdi3 (tmp, operands[1], mul));
! emit_move_insn (operands[0], tmp);
DONE;
})
--- 1163,1189 ----
})
(define_expand "umoddi3_dft"
! [(parallel [(set (match_operand:DI 0 "register_operand" "")
! (umod:DI (match_operand:DI 1 "register_operand" "")
! (match_operand:DI 2 "register_operand" "")))
(clobber (reg:DI 23))
! (clobber (reg:DI 28))])]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
"")
(define_expand "umoddi3_umk"
! [(use (match_operand:DI 0 "register_operand" ""))
! (use (match_operand:DI 1 "register_operand" ""))
! (use (match_operand:DI 2 "register_operand" ""))]
"TARGET_ABI_UNICOSMK"
{
! rtx div, mul = gen_reg_rtx (DImode);
div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
NULL_RTX, 1, OPTAB_LIB);
div = force_reg (DImode, div);
emit_insn (gen_muldi3 (mul, operands[2], div));
! emit_insn (gen_subdi3 (operands[0], operands[1], mul));
DONE;
})
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1203,1248 ****
;; expanded by the assembler.
(define_insn "*divmodsi_internal_er"
! [(set (reg:DI 27)
! (sign_extend:DI (match_operator:SI 0 "divmod_operator"
! [(reg:DI 24) (reg:DI 25)])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
! "ldq $27,__%E0($29)\t\t!literal!%#\;jsr $23,($27),__%E0\t\t!lituse_jsr!%#"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmodsi_internal"
! [(set (reg:DI 27)
! (sign_extend:DI (match_operator:SI 0 "divmod_operator"
! [(reg:DI 24) (reg:DI 25)])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "%E0 $24,$25,$27"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmoddi_internal_er"
! [(set (reg:DI 27)
! (match_operator:DI 0 "divmod_operator"
! [(reg:DI 24) (reg:DI 25)]))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
! "ldq $27,__%E0($29)\t\t!literal!%#\;jsr $23,($27),__%E0\t\t!lituse_jsr!%#"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmoddi_internal"
! [(set (reg:DI 27)
! (match_operator:DI 0 "divmod_operator"
! [(reg:DI 24) (reg:DI 25)]))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "%E0 $24,$25,$27"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
--- 1191,1240 ----
;; expanded by the assembler.
(define_insn "*divmodsi_internal_er"
! [(set (match_operand:DI 0 "register_operand" "=c")
! (sign_extend:DI (match_operator:SI 3 "divmod_operator"
! [(match_operand:DI 1 "register_operand" "a")
! (match_operand:DI 2 "register_operand" "b")])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
! "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmodsi_internal"
! [(set (match_operand:DI 0 "register_operand" "=c")
! (sign_extend:DI (match_operator:SI 3 "divmod_operator"
! [(match_operand:DI 1 "register_operand" "a")
! (match_operand:DI 2 "register_operand" "b")])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "%E3 %1,%2,%0"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmoddi_internal_er"
! [(set (match_operand:DI 0 "register_operand" "=c")
! (match_operator:DI 3 "divmod_operator"
! [(match_operand:DI 1 "register_operand" "a")
! (match_operand:DI 2 "register_operand" "b")]))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
! "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmoddi_internal"
! [(set (match_operand:DI 0 "register_operand" "=c")
! (match_operator:DI 3 "divmod_operator"
! [(match_operand:DI 1 "register_operand" "a")
! (match_operand:DI 2 "register_operand" "b")]))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
! "%E3 %1,%2,%0"
[(set_attr "type" "jsr")
(set_attr "length" "8")])