[PATCH]: Fix some constraints in m68hc11.md

[Stephane Carrez <Stephane dot Carrez at worldnet dot fr>]

Hi!

I've integrated the following patch in 3_0 branch and mainline to fix
some constraints of m68hc11 patterns.  This repairs the build of f77 runtime
libraries for HC11/HC12.

	Stephane

2001-09-30  Stephane Carrez  <Stephane.Carrez@worldnet.fr>

	* config/m68hc11/m68hc11.md ("cmpqi_1"): Fix constraints.
	("tsthi_1"): Avoid allocation in register y.
	("*movqi_68hc12"): Reorganize and fix constraints.
	("zero_extendqisi2"): Prefer d over x and y for operand 1.
	("addqi3"): Likewise.
	("addhi3"): Fix constraints.
	("*logicalhi3_zexthi"): Disparage soft registers.
Index: config/m68hc11/m68hc11.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.md,v
retrieving revision 1.17
diff -u -p -r1.17 m68hc11.md
--- m68hc11.md	2001/08/04 11:26:17	1.17
+++ m68hc11.md	2001/09/30 17:29:27
@@ -170,7 +170,7 @@
 
 (define_insn "tsthi_1"
   [(set (cc0)
-	(match_operand:HI 0 "tst_operand" "dx,y"))]
+	(match_operand:HI 0 "tst_operand" "dx,*y"))]
   ""
   "*
 {
@@ -484,8 +484,8 @@
 
 (define_insn "cmpqi_1"
   [(set (cc0)
-	(compare (match_operand:QI 0 "tst_operand" "d,m,d,!u,*B,d")
-		 (match_operand:QI 1 "cmp_operand" "im,d,!u,d,?dim*B,*u")))]
+	(compare (match_operand:QI 0 "tst_operand" "d,m,d,!u,*B,d*B")
+		 (match_operand:QI 1 "cmp_operand" "im,d,!u,d,dim*A,*u")))]
   ""
   "*
 {
@@ -1002,8 +1002,10 @@
 }")
 
 (define_insn "*movqi_68hc12"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d*AuU*q,d*A*qu,d*A*q,m,m")
-	(match_operand:QI 1 "general_operand" "rui*q,U,m,d*q,!A"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" 
+				"=d*AU*q,d*A*q,*u,d*A*q,m,m")
+	(match_operand:QI 1 "general_operand" 
+				"*ri*q,U,*ri*qU,m,d*q,!A"))]
   "TARGET_M6812"
   "*
 {
@@ -1270,9 +1272,9 @@
 }")
 
 (define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "non_push_operand" "=D,m,u")
+  [(set (match_operand:SI 0 "non_push_operand" "=D,D,m,m,u")
       (zero_extend:SI 
-	  (match_operand:QI 1 "nonimmediate_operand" "dxymu,dxy,dxy")))]
+	  (match_operand:QI 1 "nonimmediate_operand" "dmu,xy,d,xy,dxy")))]
   ""
   "#")
 
@@ -2307,7 +2309,7 @@
   "")
 
 (define_insn "*addhi3"
-  [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d")
+  [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d*A")
 	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0")
 		 (match_operand:HI 2 "general_operand" "N,i,I,mi*A*d,!u*d*w")))]
   "TARGET_M6811"
@@ -2430,9 +2432,9 @@
   "")
 
 (define_insn "addqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=!*rm,dq*A")
-        (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:QI 2 "general_operand" "N,ium*A*d")))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=!d*rm,dq,!*A")
+        (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+                 (match_operand:QI 2 "general_operand" "N,ium*A*d,ium*A*d")))]
   ""
   "*
 {
@@ -3451,11 +3453,11 @@
   "#")
 
 (define_insn "*logicalhi3_zexthi"
-  [(set (match_operand:HI 0 "register_operand" "=d")
+  [(set (match_operand:HI 0 "register_operand" "=d,d")
 	(match_operator:HI 3 "m68hc11_logical_operator"
 		[(zero_extend:HI
-		     (match_operand:QI 1 "general_operand" "imud"))
-		 (match_operand:HI 2 "general_operand" "dimu")]))]
+		     (match_operand:QI 1 "general_operand" "imd*A,?u"))
+		 (match_operand:HI 2 "general_operand" "dim,?dimu")]))]
   ""
   "#")