Re: new cpu's for rs6000 target

[Daniel Egger <egger at suse dot de>]

On Sam, 2001-09-22 at 00:33, Richard Henderson wrote:

> No.  You should only have a non-zero value here if the unit
> is not fully pipelined.  E.g. a 4 stage pipeline and only 2
> instructions may be executing on the pipeline at once.

Ah, thanks for clarifying this. So for a 3 stage pipelined fpu
which can (in theory) execute have all 3 stages working on insns
at the same time I set simultanity to 0 and the delays to 3 1?

--
Servus,
       Daniel