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Add -mno-fused-madd for mips
- To: gcc-patches at gcc dot gnu dot org
- Subject: Add -mno-fused-madd for mips
- From: Geoffrey Keating <geoffk at thief dot cygnus dot com>
- Date: Sun, 19 Aug 2001 14:39:41 -0700
- Reply-to: geoffk at redhat dot com
This patch adds the -mno-fused-madd flag to mips, based on the similar
flag for powerpc.
Tested on mips-elf (the testsuite doesn't run very well on this target
at present, but it does build and I checked that the flag works by
hand).
--
Geoff Keating <geoffk@redhat.com>
===File ~/patches/gcc-fusedmadd.patch=======================
2001-08-19 Geoffrey Keating <geoffk@redhat.com>
* doc/invoke.texi (MIPS Options): Document -mfused-madd.
* config/mips/mips.h (MASK_NO_FUSED_MADD): New.
(TARGET_FUSED_MADD): New.
(TARGET_SWITCHES): Add -mfused-madd, -mno-fused-madd.
* config/mips/mips.md: Add TARGET_FUSED_MADD as condition to
the multiply-add instructions.
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.46
diff -p -u -p -r1.46 invoke.texi
--- invoke.texi 2001/08/18 21:02:43 1.46
+++ invoke.texi 2001/08/19 21:36:39
@@ -450,7 +450,8 @@ in the following sections.
@gccoptlist{
-mabicalls -march=@var{cpu-type} -mtune=@var{cpu=type} @gol
-mcpu=@var{cpu-type} -membedded-data -muninit-const-in-rodata @gol
--membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol
+-membedded-pic -mfp32 -mfp64 -mfused-madd -mno-fused-madd @gol
+-mgas -mgp32 -mgp64 @gol
-mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol
-mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol
-mmips-as -mmips-tfile -mno-abicalls @gol
@@ -7079,6 +7080,18 @@ the default.
@opindex mfp64
Assume that 32 64-bit floating point registers are available. This is
the default when the @option{-mips3} option is used.
+
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Generate code that uses (does not use) the floating point multiply and
+accumulate instructions, when they are available. These instructions
+are generated by default if they are available, but this may be
+undesirable if the extra precision causes problems or on certain chips
+in the mode where denormals are rounded to zero where denormals
+generated by multiply and accumulate instructions cause exceptions
+anyway.
@item -mgp32
@opindex mgp32
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.128
diff -p -u -p -r1.128 mips.h
--- mips.h 2001/08/18 20:25:53 1.128
+++ mips.h 2001/08/19 21:36:39
@@ -223,6 +223,8 @@ extern void sbss_section PARAMS ((void)
#define MASK_UNINIT_CONST_IN_RODATA \
0x00800000 /* Store uninitialized
consts in rodata */
+#define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
+ multiply-add operations. */
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
@@ -311,6 +313,8 @@ extern void sbss_section PARAMS ((void)
#define TARGET_MAD (target_flags & MASK_MAD)
+#define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
+
#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
@@ -439,6 +443,10 @@ extern void sbss_section PARAMS ((void)
N_("Use multiply accumulate")}, \
{"no-mad", -MASK_MAD, \
N_("Don't use multiply accumulate")}, \
+ {"no-fused-madd", MASK_NO_FUSED_MADD, \
+ N_("Don't generate fused multiply/add instructions")}, \
+ {"fused-madd", -MASK_NO_FUSED_MADD, \
+ N_("Generate fused multiply/add instructions")}, \
{"fix4300", MASK_4300_MUL_FIX, \
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.106
diff -p -u -p -r1.106 mips.md
--- mips.md 2001/08/18 11:23:01 1.106
+++ mips.md 2001/08/19 21:36:41
@@ -2138,7 +2138,7 @@
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
"madd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
@@ -2148,7 +2148,7 @@
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
"madd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
@@ -2158,7 +2158,7 @@
(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
"msub.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
@@ -2169,7 +2169,7 @@
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
+ "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
@@ -2179,7 +2179,7 @@
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
"nmadd.d\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
@@ -2189,7 +2189,7 @@
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT"
+ "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
"nmadd.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
@@ -2199,7 +2199,7 @@
(minus:DF (match_operand:DF 1 "register_operand" "f")
(mult:DF (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
"nmsub.d\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "DF")])
@@ -2209,7 +2209,7 @@
(minus:SF (match_operand:SF 1 "register_operand" "f")
(mult:SF (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT"
+ "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
"nmsub.s\\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "SF")])
============================================================