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mips works for mips{5,32,64}
- To: gcc-patches at gcc dot gnu dot org
- Subject: mips works for mips{5,32,64}
- From: mike stump <mrs at windriver dot com>
- Date: Thu, 28 Jun 2001 16:36:21 -0700 (PDT)
I submitted this before:
http://gcc.gnu.org/ml/gcc-patches/2001-06/msg00513.html
I thought I'd timeout and send another ping and see if anyone will
ok this work.
I improved it a tad since the first submission and incorporated
solutions for all the problems and comments I received.
2001-06-08 Mike Stump <mrs@wrs.com>
* mips.c (override_options): Add support for -mips5, -mips32
and -mips64.
* mips.h (ISA_HAS_64BIT_REGS, ISA_HAS_CONDMOVE, ISA_HAS_8CC,
ISA_HAS_FP4): Likewise.
* mips.md (*mul_add_di, *mul_add_si, *mul_sub_di, *mul_sub_si): Add.
Doing diffs in .:
*** ./mips.c.~1~ Mon Jun 4 19:59:54 2001
--- ./mips.c Fri Jun 8 15:42:06 2001
*************** int mips_abi;
*** 206,212 ****
/* Strings to hold which cpu and instruction set architecture to use. */
const char *mips_cpu_string; /* for -mcpu=<xxx> */
! const char *mips_isa_string; /* for -mips{1,2,3,4} */
const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
/* Whether we are generating mips16 code. This is a synonym for
--- 206,212 ----
/* Strings to hold which cpu and instruction set architecture to use. */
const char *mips_cpu_string; /* for -mcpu=<xxx> */
! const char *mips_isa_string; /* for -mips{1,2,3,4,5,32 (6), 64 (7)} */
const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
/* Whether we are generating mips16 code. This is a synonym for
*************** const_float_1_operand (op, mode)
*** 642,649 ****
REAL_VALUE_FROM_CONST_DOUBLE (d, op);
! /* We only initialize these values if we need them, since we will
! never get called unless mips_isa >= 4. */
if (! one_initialized)
{
onedf = REAL_VALUE_ATOF ("1.0", DFmode);
--- 642,648 ----
REAL_VALUE_FROM_CONST_DOUBLE (d, op);
! /* We only initialize these values if we need them. */
if (! one_initialized)
{
onedf = REAL_VALUE_ATOF ("1.0", DFmode);
*************** override_options ()
*** 4739,4745 ****
mips_isa = MIPS_ISA_DEFAULT;
}
}
! else if (mips_isa < 1 || mips_isa > 4)
{
error ("-mips%d not supported", mips_isa);
mips_isa = 1;
--- 4738,4752 ----
mips_isa = MIPS_ISA_DEFAULT;
}
}
! else if (mips_isa == 32)
! {
! mips_isa = MIPS32;
! }
! else if (mips_isa == 64)
! {
! mips_isa = MIPS64;
! }
! else if (mips_isa < 1 || mips_isa > 5)
{
error ("-mips%d not supported", mips_isa);
mips_isa = 1;
*************** override_options ()
*** 4842,4847 ****
--- 4849,4855 ----
mips_cpu = PROCESSOR_R3000;
break;
case 2:
+ case MIPS32:
mips_cpu_string = "6000";
mips_cpu = PROCESSOR_R6000;
break;
*************** override_options ()
*** 4850,4855 ****
--- 4858,4865 ----
mips_cpu = PROCESSOR_R4000;
break;
case 4:
+ case 5:
+ case MIPS64:
mips_cpu_string = "8000";
mips_cpu = PROCESSOR_R8000;
break;
*************** override_options ()
*** 4945,4951 ****
}
if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
! || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
--- 4955,4964 ----
}
if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
! || (mips_cpu == PROCESSOR_R6000
! && mips_isa != 1
! && mips_isa != 2
! && mips_isa != MIPS32)
|| ((mips_cpu == PROCESSOR_R4000
|| mips_cpu == PROCESSOR_R4100
|| mips_cpu == PROCESSOR_R4300
*** ./mips.h.~1~ Mon Jun 4 19:59:52 2001
--- ./mips.h Thu Jun 28 16:14:55 2001
*************** enum mips_abicalls_type {
*** 100,105 ****
--- 100,108 ----
MIPS_ABICALLS_YES
};
+ #define MIPS32 6
+ #define MIPS64 7
+
/* Recast the abicalls class to be the abicalls attribute. */
#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
*************** extern int mips16; /* whether generati
*** 140,146 ****
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
! extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */
extern const char *mips_no_mips16_string;/* for -mno-mips16 */
--- 143,149 ----
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
! extern const char *mips_isa_string; /* for -mips{1,2,3,4,5,32 (6),64 (7)} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */
extern const char *mips_no_mips16_string;/* for -mno-mips16 */
*************** extern void sbss_section PARAMS ((void)
*** 521,527 ****
# if MIPS_ISA_DEFAULT == 4
# define MULTILIB_ISA_DEFAULT "mips4"
# else
! # define MULTILIB_ISA_DEFAULT "mips1"
# endif
# endif
# endif
--- 524,542 ----
# if MIPS_ISA_DEFAULT == 4
# define MULTILIB_ISA_DEFAULT "mips4"
# else
! # if MIPS_ISA_DEFAULT == 5
! # define MULTILIB_ISA_DEFAULT "mips5"
! # else
! # if MIPS_ISA_DEFAULT == 6
! # define MULTILIB_ISA_DEFAULT "mips32"
! # else
! # if MIPS_ISA_DEFAULT == 7
! # define MULTILIB_ISA_DEFAULT "mips64"
! # else
! # define MULTILIB_ISA_DEFAULT "mips1"
! # endif
! # endif
! # endif
# endif
# endif
# endif
*************** extern void sbss_section PARAMS ((void)
*** 590,607 ****
depending on the instruction set architecture level. */
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
! #define HAVE_SQRT_P() (mips_isa != 1)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
! #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
)
/* ISA has branch likely instructions (eg. mips2). */
! #define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
/* ISA has the conditional move instructions introduced in mips4. */
! #define ISA_HAS_CONDMOVE (mips_isa == 4 \
! )
/* ISA has just the integer condition move instructions (movn,movz) */
#define ISA_HAS_INT_CONDMOVE 0
--- 605,623 ----
depending on the instruction set architecture level. */
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
! #define HAVE_SQRT_P() (mips_isa >= 2)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
! #define ISA_HAS_64BIT_REGS (mips_isa >= 3 \
! && mips_isa != MIPS32 \
)
/* ISA has branch likely instructions (eg. mips2). */
! #define ISA_HAS_BRANCHLIKELY (mips_isa >= 2 && mips_isa < MIPS64)
/* ISA has the conditional move instructions introduced in mips4. */
! #define ISA_HAS_CONDMOVE (mips_isa >= 4 \
! )
/* ISA has just the integer condition move instructions (movn,movz) */
#define ISA_HAS_INT_CONDMOVE 0
*************** extern void sbss_section PARAMS ((void)
*** 610,633 ****
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
! #define ISA_HAS_8CC (mips_isa == 4 \
)
! /* This is a catch all for the other new mips4 instructions: indexed load and
! indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
! and the FP recip and recip sqrt instructions */
! #define ISA_HAS_FP4 (mips_isa == 4 \
)
/* ISA has conditional trap instructions. */
#define ISA_HAS_COND_TRAP (mips_isa >= 2)
! /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
! -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
! -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
! target_flags, and -mgp64 sets MASK_64BIT.
Setting MASK_64BIT in target_flags will cause gcc to assume that
registers are 64 bits wide. int, long and void * will be 32 bit;
--- 626,651 ----
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
! #define ISA_HAS_8CC (mips_isa >= 4 \
)
! /* This is a catch all for the other new mips4 instructions: indexed
! load and indexed prefetch instructions, the FP madd,msub,nmadd, and
! nmsub instructions, and the FP recip and recip sqrt instructions */
! #define ISA_HAS_FP4 (mips_isa >= 4 \
! && mips_isa != MIPS32 \
)
/* ISA has conditional trap instructions. */
#define ISA_HAS_COND_TRAP (mips_isa >= 2)
! /* CC1_SPEC causes -mips3, -mips4, -mips5 and mips64 to set -mfp64 and
! -mgp64; -mips1, -mips2 and -mips32 sets -mfp32 and -mgp32. This
! can be overridden by an explicit -mfp32, -mfp64, -mgp32 or -mgp64.
! -mfp64 sets MASK_FLOAT64 in target_flags, and -mgp64 sets
! MASK_64BIT.
Setting MASK_64BIT in target_flags will cause gcc to assume that
registers are 64 bits wide. int, long and void * will be 32 bit;
*************** while (0)
*** 777,783 ****
than gas. */
#define MIPS_AS_ASM_SPEC "\
! %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
%{pipe: %e-pipe is not supported.} \
%{K} %(subtarget_mips_as_asm_spec)"
--- 795,801 ----
than gas. */
#define MIPS_AS_ASM_SPEC "\
! %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} %{mips1} %{mips2} %{mips3} %{mips4} %{mips5} \
%{pipe: %e-pipe is not supported.} \
%{K} %(subtarget_mips_as_asm_spec)"
*************** while (0)
*** 841,847 ****
/* ASM_SPEC is the set of arguments to pass to the assembler. */
#define ASM_SPEC "\
! %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
--- 859,865 ----
/* ASM_SPEC is the set of arguments to pass to the assembler. */
#define ASM_SPEC "\
! %{!membedded-pic:%{G*}} %(endian_spec) \
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
*************** while (0)
*** 914,925 ****
#ifndef CC1_SPEC
#define CC1_SPEC "\
%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
! %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
! %{mint64|mlong64|mlong32:-mexplicit-type-size }\
%{m4650:-mcpu=r4650} \
%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
--- 932,945 ----
#ifndef CC1_SPEC
#define CC1_SPEC "\
%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
! %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips32:-mfp32 -mgp32} \
%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+ %{mips5:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+ %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
! %{mint64|mlong64|mlong32:-mexplicit-type-size } \
%{m4650:-mcpu=r4650} \
%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
*************** extern enum reg_class mips_regno_to_clas
*** 1919,1925 ****
'h' Hi register
'l' Lo register
'x' Multiply/divide registers
! 'a' HILO_REG
'z' FP Status register
'b' All registers */
--- 1939,1945 ----
'h' Hi register
'l' Lo register
'x' Multiply/divide registers
! 'a' HILO_REG (a 64 bit result split across Hi/Lo in 64BIT mode)
'z' FP Status register
'b' All registers */
*** ./mips.md.~1~ Mon Jun 4 20:00:37 2001
--- ./mips.md Fri Jun 8 17:44:04 2001
***************
*** 1775,1780 ****
--- 1775,1846 ----
;; Multiply-accumulate patterns
+ (define_insn "*mul_add_di"
+ [(set (match_operand:DI 0 "register_operand" "=x")
+ (plus:DI (mult:DI (match_operator:DI 4 "extend_operator"
+ [(match_operand:SI 1 "register_operand" "d")])
+ (match_operator:DI 5 "extend_operator"
+ [(match_operand:SI 2 "register_operand" "d")]))
+ (match_operand:DI 3 "register_operand" "0")))
+ (clobber (match_scratch:SI 6 "=a"))]
+ "mips_isa >= MIPS32 && !TARGET_MIPS16
+ && GET_CODE (operands[4]) == GET_CODE (operands[5])"
+ "*
+ {
+ if (GET_CODE (operands[4]) == SIGN_EXTEND)
+ return \"madd\\t%1,%2\";
+ return \"maddu\\t%1,%2\";
+ }"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
+ (define_insn "*mul_add_si"
+ [(set (match_operand:SI 0 "register_operand" "=l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))
+ (match_operand:SI 3 "register_operand" "0")))
+ (clobber (match_scratch:SI 4 "=a"))
+ (clobber (match_scratch:SI 5 "=h"))]
+ "mips_isa >= MIPS32 && !TARGET_MIPS16"
+ "madd\\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
+ (define_insn "*mul_sub_di"
+ [(set (match_operand:DI 0 "register_operand" "=x")
+ (minus:DI (match_operand:DI 3 "register_operand" "0")
+ (mult:DI (match_operator:DI 4 "extend_operator"
+ [(match_operand:SI 1 "register_operand" "d")])
+ (match_operator:DI 5 "extend_operator"
+ [(match_operand:SI 2 "register_operand" "d")]))))
+ (clobber (match_scratch:SI 6 "=a"))]
+ "mips_isa >= MIPS32 && !TARGET_MIPS16
+ && GET_CODE (operands[4]) == GET_CODE (operands[5])"
+ "*
+ {
+ if (GET_CODE (operands[4]) == SIGN_EXTEND)
+ return \"msub\\t%1,%2\";
+ return \"msubu\\t%1,%2\";
+ }"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
+ (define_insn "*mul_sub_si"
+ [(set (match_operand:SI 0 "register_operand" "=l")
+ (minus:SI (match_operand:SI 3 "register_operand" "0")
+ (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:SI 4 "=a"))
+ (clobber (match_scratch:SI 5 "=h"))]
+ "mips_isa >= MIPS32 && !TARGET_MIPS16"
+ "msub\\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")
+ (set_attr "length" "4")])
+
;; For processors that can copy the output to a general register:
;;
;; The all-d alternative is needed because the combiner will find this
***************
*** 1785,1791 ****
;; "?" to the constraint is too strong, and causes values to be loaded into
;; LO even when that's more costly. For now, using "*d" mostly does the
;; trick.
! (define_insn "*mul_acc_si"
[(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
(match_operand:SI 2 "register_operand" "d,d,d"))
--- 1851,1857 ----
;; "?" to the constraint is too strong, and causes values to be loaded into
;; LO even when that's more costly. For now, using "*d" mostly does the
;; trick.
! (define_insn "*mul_acc_si_3900"
[(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
(match_operand:SI 2 "register_operand" "d,d,d"))
*************** move\\t%0,%z4\\n\\
*** 3141,3149 ****
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set (attr "length")
! (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
--- 3207,3215 ----
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set (attr "length")
! (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
*************** move\\t%0,%z4\\n\\
*** 3225,3232 ****
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
--- 3291,3298 ----
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
*************** move\\t%0,%z4\\n\\
*** 3242,3250 ****
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set (attr "length")
! (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
--- 3308,3316 ----
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set (attr "length")
! (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
*************** move\\t%0,%z4\\n\\
*** 3326,3333 ****
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
--- 3392,3399 ----
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
*************** move\\t%0,%z4\\n\\
*** 3343,3351 ****
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set (attr "length")
! (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
--- 3409,3417 ----
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set (attr "length")
! (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
*************** move\\t%0,%z4\\n\\
*** 3420,3427 ****
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
--- 3486,3493 ----
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d")
*************** move\\t%0,%z4\\n\\
*** 3497,3504 ****
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
--- 3563,3570 ----
(set_attr "mode" "DI")
(set (attr "length")
(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
! (const_int 4)
! (const_int 8)))])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
--------------