Further docu patches for XX-bit

[Andreas Jaeger <aj at suse dot de>]

Ok for the mainline?  Shall I add this also to the branch?

Now the manual should be consistent,
Andreas

2001-04-28  Andreas Jaeger  <aj@suse.de>

	* invoke.texi: Use XX-bit instead of XXbit or XX bit where
	appropriate.
	* extend.texi: Likewise.
	* tm.texi: Likewise.

Index: invoke.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/invoke.texi,v
retrieving revision 1.294
diff -u -r1.294 invoke.texi
--- invoke.texi	2001/04/28 08:08:03	1.294
+++ invoke.texi	2001/04/28 10:34:01
@@ -4965,7 +4965,7 @@
 @end table
 
 These @samp{-m} switches are supported in addition to the above
-on SPARC V9 processors in 64 bit environments.
+on SPARC V9 processors in 64-bit environments.
 
 @table @gcctabopt
 @item -mlittle-endian
@@ -4973,9 +4973,9 @@
 
 @item -m32
 @itemx -m64
-Generate code for a 32 bit or 64 bit environment.
-The 32 bit environment sets int, long and pointer to 32 bits.
-The 64 bit environment sets int to 32 bits and long and pointer
+Generate code for a 32-bit or 64-bit environment.
+The 32-bit environment sets int, long and pointer to 32 bits.
+The 64-bit environment sets int to 32 bits and long and pointer
 to 64 bits.
 
 @item -mcmodel=medlow
@@ -4997,9 +4997,9 @@
 
 @item -mcmodel=embmedany
 Generate code for the Medium/Anywhere code model for embedded systems:
-assume a 32 bit text and a 32 bit data segment, both starting anywhere
+assume a 32-bit text and a 32-bit data segment, both starting anywhere
 (determined at link time).  Register %g4 points to the base of the
-data segment.  Pointers still 64 bits.
+data segment.  Pointers are still 64 bits.
 Programs are statically linked, PIC is not supported.
 
 @item -mstack-bias
@@ -5609,12 +5609,12 @@
 @code{model} attribute.
 
 @item -mcode-model=medium
-Assume objects may be anywhere in the 32 bit address space (the compiler
+Assume objects may be anywhere in the 32-bit address space (the compiler
 will generate @code{seth/add3} instructions to load their addresses), and
 assume all subroutines are reachable with the @code{bl} instruction.
 
 @item -mcode-model=large
-Assume objects may be anywhere in the 32 bit address space (the compiler
+Assume objects may be anywhere in the 32-bit address space (the compiler
 will generate @code{seth/add3} instructions to load their addresses), and
 assume subroutines may not be reachable with the @code{bl} instruction
 (the compiler will generate the much slower @code{seth/add3/jl}
@@ -6408,7 +6408,7 @@
 ISA level.
 
 @item -mips3
-Issue instructions from level 3 of the MIPS ISA (64 bit instructions).
+Issue instructions from level 3 of the MIPS ISA (64-bit instructions).
 @samp{r4000} is the default @var{cpu type} at this ISA level.
 
 @item -mips4
@@ -6747,7 +6747,7 @@
 @item -mno-wide-multiply
 @itemx -mwide-multiply
 Control whether GCC uses the @code{mul} and @code{imul} that produce
-64 bit results in @code{eax:edx} from 32 bit operands to do @code{long
+64-bit results in @code{eax:edx} from 32-bit operands to do @code{long
 long} multiplies and 32-bit division by constants.
 
 @item -mrtd
@@ -7383,7 +7383,7 @@
 Compile code for the processor in little endian mode.
 
 @item -mdalign
-Align doubles at 64 bit boundaries.  Note that this changes the calling
+Align doubles at 64-bit boundaries.  Note that this changes the calling
 conventions, and thus some functions from the standard C library will
 not work unless you recompile it first with -mdalign.
 
Index: extend.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/extend.texi,v
retrieving revision 1.95
diff -u -r1.95 extend.texi
--- extend.texi	2001/03/23 01:49:08	1.95
+++ extend.texi	2001/04/28 10:34:08
@@ -1940,11 +1940,11 @@
 addresses can be loaded with the @code{ld24} instruction), and are
 callable with the @code{bl} instruction.
 
-Medium model objects may live anywhere in the 32 bit address space (the
+Medium model objects may live anywhere in the 32-bit address space (the
 compiler will generate @code{seth/add3} instructions to load their addresses),
 and are callable with the @code{bl} instruction.
 
-Large model objects may live anywhere in the 32 bit address space (the
+Large model objects may live anywhere in the 32-bit address space (the
 compiler will generate @code{seth/add3} instructions to load their addresses),
 and may not be reachable with the @code{bl} instruction (the compiler will
 generate the much slower @code{seth/add3/jl} instruction sequence).
@@ -2514,7 +2514,7 @@
 Small model objects live in the lower 16MB of memory (so that their
 addresses can be loaded with the @code{ld24} instruction).
 
-Medium and large model objects may live anywhere in the 32 bit address space
+Medium and large model objects may live anywhere in the 32-bit address space
 (the compiler will generate @code{seth/add3} instructions to load their
 addresses).
 
Index: tm.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/tm.texi,v
retrieving revision 1.182
diff -u -r1.182 tm.texi
--- tm.texi	2001/04/27 19:59:53	1.182
+++ tm.texi	2001/04/28 10:34:23
@@ -5698,7 +5698,7 @@
 @itemx UNALIGNED_INT_ASM_OP
 @itemx UNALIGNED_DOUBLE_INT_ASM_OP
 A C string constant, including spacing, giving the pseudo-op to use 
-to assemble 16, 32, and 64 bit integers respectively @emph{without}
+to assemble 16-, 32-, and 64-bit integers respectively @emph{without}
 adding implicit padding or alignment.  These macros are required if
 DWARF 2 frame unwind is used.  On ELF systems, these will default
 to @code{.2byte}, @code{.4byte}, and @code{.8byte}.@refill

-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj